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isp1362 single-chip universal serial bus on-the-go controller rev. 04 ?24 december 2004 product data 1. general description the isp1362 is a single-chip universal serial bus (usb) on-the-go (otg) controller integrated with the advanced philips slave host controller (pshc) and the philips isp1181b device controller (dc). the usb otg controller is compliant with on-the-go supplement to the usb 2.0 speci?ation rev. 1.0a . the host and device controllers are compliant with universal serial bus speci?ation rev. 2.0, supporting data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the isp1362 has two usb ports: port 1 and port 2. port 1 can be hardware con?ured to function as a downstream port, an upstream port or an otg port whereas port 2 can only be used as a downstream port. the otg port can switch roles from host to peripheral, or from peripheral to host. the otg port can become a host through the host negotiation protocol (hnp) as speci?d in the otg supplement. a usb product with otg capability can function either as a host or as a peripheral. for instance, with this dual-role capability, a personal computer (pc) peripheral such as a printer may switch roles from a peripheral to a host for connecting to a digital camera so that the printer can print pictures taken by the camera without using a pc. when a usb product with otg capability is inactive, the usb interface is turned off. this feature has made otg a technology well-suited for use in portable devices?uch as, personal digital assistant (pda), digital still camera (dsc) and mobile phone?n which power consumption is a concern. the isp1362 is an otg controller designed to perform such functions. 2. features complies fully with: universal serial bus speci?ation rev. 2.0 on-the-go supplement to the usb 2.0 speci?ation rev. 1.0a supports data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s) adapted from open host controller interface speci?ation for usb release 1.0a usb otg: supports host negotiation protocol (hnp) and session request protocol (srp) for otg dual-role devices provides status and control signals for software implementation of hnp and srp provides programmable timers required for hnp and srp supports built-in and external source of v bus output current of the built-in charge pump is adjustable by using an external capacitor
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 ?24 december 2004 2 of 150 9397 750 13957 ?koninklijke philips electronics n.v. 2004. all rights reserved. usb host: supports integrated physical 4096 bytes of multicon?uration memory supports all four types of usb transfers: control, bulk, interrupt and isochronous supports multiframe buffering for isochronous transfer supports automatic interrupt polling rate mechanism supports paired buffering for bulk transfer directly addressable memory architecture; memory can be updated on-the-? usb device: supports high performance usb interface device with integrated serial interface engine (sie), buffer memory and transceiver supports fully autonomous and multicon?uration dma operation supports up to 14 programmable usb endpoints with 2 xed control in/out endpoints supports integrated physical 2462 bytes of multicon?uration memory supports endpoints with double buffering to increase throughput and ease real-time data transfer supports controllable lazyclock (110 khz 50 %) output during ?uspend supports two usb ports: port 1 and port 2 port 1 can be con?ured to function as a downstream port, an upstream port or an otg port port 2 can be used only as a downstream port supports software-controlled connection to the usb bus (softconnect) supports good usb connection indicator that blinks with traf? (goodlink) complies with usb power management requirements supports internal power-on and low-voltage reset circuit, with possibility of a software reset supports operation over the extended usb voltage range (4.0 v to 5.5 v) with 5 v tolerant i/o pads high-speed parallel interface to most cpus available in the market, such as hitachi sh-3, intel strongarm , philips xa, fujitsu sparclite , nec and toshiba mips, arm7/9, motorola dragonball and powerpc reduced instruction set computer (risc): 16-bit data bus 10 mbyte/s data transfer rate between the microprocessor and isp1362 supports programmed i/o (pio) or direct memory access (dma) supports ?uspend?and remote wake-up uses 12 mhz crystal or direct clock source with on-chip phase-locked loop (pll) for low electro-magnetic interference (emi) operates at 3.3 v power supply operating temperature range from ? 40 cto + 85 c available in 64-pin lqfp and tfbga packages.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 ?24 december 2004 3 of 150 9397 750 13957 ?koninklijke philips electronics n.v. 2004. all rights reserved. 3. applications the isp1362 can be used to implement a dual-role usb device in any application?sb host or usb peripheral?epending on the cable connection. if the dual-role device is connected to a typical usb peripheral, it behaves like a typical usb host. the dual-role device, however, can also be connected to a pc or any other usb host and behave like a typical usb peripheral. 3.1 host/peripheral roles mobile phone to/from: mobile phone: exchange contact information digital still camera: e-mail pictures or upload pictures to the web mp3 player: upload, download and broadcast music mass storage: upload and download ?es scanner: scan business cards digital still camera to/from: digital still camera: exchange pictures mobile phone: e-mail pictures, upload pictures to the web printer: print pictures mass storage: store pictures printer to/from: digital still camera: print pictures scanner: print scanned image mass storage: print ?es stored in a device mp3 player to/from: mp3 player: exchange songs mass storage: upload and download songs oscilloscope to/from: printer: print screen image personal digital assistant to/from: personal digital assistant: exchange ?es printer: print ?es mobile phone: upload and download ?es mp3 player: upload and download songs scanner: scan pictures mass storage: upload and download ?es global positioning system (gps): obtain directions, mapping information digital still camera: upload pictures oscilloscope: con?ure oscilloscope.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 ?24 december 2004 4 of 150 9397 750 13957 ?koninklijke philips electronics n.v. 2004. all rights reserved. 4. abbreviations dc device controller dma direct memory access dsc digital still camera emi electro-magnetic interference gps global positioning system hc host controller hcd host controller driver hnp host negotiation protocol otg on-the-go pda personal digital assistant pio programmed input/output pll phase-locked loop pshc philips slave host controller sie serial interface engine srp session request protocol usb universal serial bus. 5. ordering information table 1: ordering information type number package name description version ISP1362BD lqfp64 plastic low pro?e quad ?t package; 64 leads; body 10 x 10 x 1.4 mm sot314-2 isp1362ee tfbga64 plastic thin ?e-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm sot543-1 isp1362ee/01
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors isp1362 single-chip usb otg controller 9397 750 13957 ?koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 ?24 december 2004 5 of 150 6. block diagram fig 1. block diagram. 004aaa044 power-on reset hc buffer memory pll dc buffer memory overcurrent protection usb transceiver otg transceiver charge pump goodlink advanced philips slave host controller bus interface on-the-go controller philips device controller internal reset int2 int1 dreq2 test2 test1 test0 dreq1 dack2 dack1 a1 a0 wr cs rd h_suspend/ h_wakeup 2, 3, 5 to 8, 10 to 13, 15 to 18, 63, 64 20 33 32 21 22 61 62 28 29 24 25 30 31 23 59 60 reset d0 to d15 to system clock 12 mhz clkout 1, 9, 19, 27, 37, 57 4, 14, 26, 40, 52, 58 51 34 39 45 48 54 53 56 35 36 42 41 v dd_5v h_psw1 h_psw2 h_oc1 h_oc2 h_dm2 h_dp2 otg_dm1 otg_dp1 v bus 46 47 49 50 55 16 dgnd agnd gl otgmode cp_cap2 cp_cap1 id d_suspend/ d_wakeup v cc 44 43 x2 x1 38 isp1362
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 6 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. pinning information 7.1 pinning fig 2. pin con guration lqfp64. ISP1362BD 004aaa050 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 d1 d0 a1 a0 test2 test1 v cc dgnd v dd_5v v bus cp_cap2 cp_cap1 v cc agnd otg_dp1 otg_dm1 d14 d15 dgnd rd cs wr test0 dreq1 dreq2 v cc dgnd dack1 dack2 int1 int2 reset dgnd d2 d3 v cc d4 d5 d6 d7 dgnd d8 d9 d10 d11 v cc d12 d13 id h_dp2 h_dm2 otgmode x2 x1 h_oc1 h_oc2 v cc gl clkout dgnd h_psw2 h_psw1 d_suspend/d_wakeup h_suspend/h_wakeup
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 7 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 3. pin con guration tfbga64. a b c d e f h j k g 2468910 1357 isp1362ee 004aaa151 isp1362ee/01 ball a1 index area
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 8 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2 pin description table 2: pin description symbol [1] pin lqfp64 ball tfbga64 type [2] description dgnd 1 b1 - digital ground d2 2 c2 i/o bit 2 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d3 3 c1 i/o bit 3 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output v cc 4 d2 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f d4 5 d1 i/o bit 4 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d5 6 e2 i/o bit 5 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d6 7 e1 i/o bit 6 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d7 8 f2 i/o bit 7 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output dgnd 9 f1 - digital ground d8 10 g2 i/o bit 8 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d9 11 g1 i/o bit 9 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d10 12 h2 i/o bit 10 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d11 13 h1 i/o bit 11 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 9 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. v cc 14 j2 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f d12 15 j1 i/o bit 12 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d13 16 k1 i/o bit 13 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d14 17 k2 i/o bit 14 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d15 18 j3 i/o bit 15 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output dgnd 19 k3 - digital ground rd 20 j4 i read strobe input; when asserted low, it indicates that the hc/dc driver is requesting a read to the buffer memory or the internal registers of the hc/dc input with hysteresis cs 21 k4 i chip select input (active low); enables the hc/dc driver to access the buffer memory and registers of the hc/dc input wr 22 j5 i write strobe input; when asserted low, it indicates that the hc/dc driver is requesting a write to the buffer memory or the internal registers of the hc/dc input with hysteresis test0 23 k5 i/o for test input and output; pulled high by a 100 k ? resistor bidirectional, push-pull input, three-state output dreq1 24 j6 o dma request output; when active, it signals the dma controller that a data transfer is requested by the hc; the active level (high or low) of the request is programmed by using the hchardwarecon guration register (20h/a0h) if the onedma bit of the hchardwarecon guration register is set to logic 1, both the hc and dc dma channel will be routed to dreq1 and d a ck1. push-pull output dreq2 25 k6 o dma request output; when active, it signals the dma controller that a data transfer is requested by the dc; the active level (high or low) of the request is programmed by using the dchardwarecon guration register (bah/bbh) push-pull output table 2: pin description continued symbol [1] pin lqfp64 ball tfbga64 type [2] description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 10 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. v cc 26 j7 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f dgnd 27 k7 - digital ground d a ck1 28 j8 i dma acknowledge input; indicates that a request for dma transfer from the hc has been granted by the dma controller; the active level (high or low) of the acknowledge signal is programmed by using the hchardwarecon guration register (20h/a0h); when not in use, this pin must be connected to v cc through a 10 k ? resistor input with hysteresis d a ck2 29 k8 i dma acknowledge input; indicates that a request for dma transfer from the dc has been granted by the dma controller; the active level (high or low) of the acknowledge signal is programmed by using the dchardwarecon guration register (bah/bbh); when not in use, this pin must be connected to v cc through a 10 k ? resistor input with hysteresis int1 30 j9 o interrupt request from the hc; provides a mechanism for the hc to interrupt the microprocessor; see hchardwarecon guration register (20h/a0h) section 15.4.1 for details if the oneint bit of the hchardwarecon guration register is set to logic 1, both the hc and dc interrupt request will be routed to int1. push-pull output int2 31 k9 o interrupt request from the dc; provides a mechanism for the dc to interrupt the microprocessor; see dchardwarecon guration register (bah/bbh) section 16.1.4 for details push-pull output reset 32 k10 i reset input input with hysteresis and internal pull-up resistor h_suspend/ h_w akeup 33 j10 i/o i/o pin (open-drain); goes high when the hc is in the suspend mode; a low pulse must be applied to this pin to wake up the hc; connect a 100 k ? resistor to v cc bidirectional, push-pull input, three-state open-drain output d_suspend/ d_w akeup 34 h9 i/o i/o pin (open-drain); goes high when the dc is in the suspend mode; a low pulse must be applied to this pin to wake up the dc; connect a 100 k ? resistor to v cc bidirectional, push-pull input, three-state open-drain output h_psw1 35 h10 o connects to the external pmos switch; required when the external charge pump or external v bus is used for providing v bus to the downstream port low switches on the pmos providing v bus to the downstream port high switches off the pmos when not in use, leave this pin open open-drain output table 2: pin description continued symbol [1] pin lqfp64 ball tfbga64 type [2] description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 11 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. h_psw2 36 g9 o connects to the external pmos switch low switches on the pmos providing v bus to the downstream port high switches off the pmos when not in use, leave this pin open open-drain output dgnd 37 g10 - digital ground clkout 38 f9 o programmable clock output; the default clock frequency is 12 mhz and can be varied from 3 mhz to 48 mhz push-pull output gl 39 f10 o goodlink led indicator output; the led is off by default, blinks on upon usb traf c open-drain output; 4 ma v cc 40 e9 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f h_oc2 41 e10 i overcurrent sense input for downstream port 2; both the digital and analog overcurrent inputs can be used for port 2, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the v dd_5v pin h_oc1 42 d9 i overcurrent sensing input for downstream port 1; both the digital and analog overcurrent inputs can be used for port 1, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the v dd_5v pin x1 43 d10 ai crystal input; connected directly to a 12 mhz crystal; when this pin is connected to an external clock oscillator, leave pin x2 open x2 44 c9 ao crystal output; connected directly to a 12 mhz crystal; when pin x1 is connected to an external clock oscillator, leave this pin open o tgmode 45 c10 i to select whether port 1 is operating in the otg or non-otg mode; see ta bl e 8 input with hysteresis h_dm2 46 b9 ai/o downstream d ? signal; host only, port 2; when not in use, leave this pin open and set bit connectpulldown_ds2 of the hchardwarecon guration register h_dp2 47 b10 ai/o downstream d+ signal; host only, port 2; when not in use, leave this pin open and set bit connectpulldown_ds2 of the hchardwarecon guration register id 48 a10 i input pin for sensing otg id; the status of this input pin is re ected in the otgstatus register (bit 0); see ta bl e 8 input with hysteresis otg_dm1 49 a9 ai/o d ? signal of the otg port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit connectpulldown_ds1 of the hchardwarecon guration register [3] otg_dp1 50 b8 ai/o d + signal of the otg port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit connectpulldown_ds1 of the hchardwarecon guration register [3] table 2: pin description continued symbol [1] pin lqfp64 ball tfbga64 type [2] description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 12 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names with an overscore (for example, name) represent active low signals. [2] all i/o pads are 5 v tolerant. [3] in the otg mode, this pin is pulled down by an internal resistor. agnd 51 a8 - analog ground; used for otg atx v cc 52 b7 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f cp_cap1 53 a7 ai/o charge pump capacitor pin 1; low esr; see section 11.6 cp_cap2 54 b6 ai/o charge pump capacitor pin 2; low esr; see section 11.6 v bus 55 a6 i/o analog input and output otg mode built-in charge pump output or v bus voltage comparators input; connect to pin v bus of the otg connector dc mode input as v bus sensing; connect to pin v bus of the upstream connector hc mode not used; leave open v dd_5v 56 b5 i supply reference voltage (5 v); to be used together with built-in overcurrent circuit; when built-in overcurrent circuit is not in use, this pin can be tied to v cc ; it is recommended to connect a decoupling capacitor of 0.01 f dgnd 57 a5 - digital ground v cc 58 b4 - supply voltage (3.3 v); it is recommended to connect a decoupling capacitor of 0.01 f test1 59 a4 i/o for test input and output, pulled to gnd by a 10 k ? resistor bidirectional, push-pull input, three-state output test2 60 b3 i/o for test input and output, pulled to gnd by a 10 k ? resistor bidirectional, push-pull input, three-state output a0 61 a3 i command or data phase input a1 62 b2 i low pio bus of the hc is selected high pio bus of the dc is selected input d0 63 a2 i/o bit 0 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output d1 64 a1 i/o bit 1 of the bidirectional data bus that connects to the internal registers and buffer memory of the isp1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output table 2: pin description continued symbol [1] pin lqfp64 ball tfbga64 type [2] description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 13 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description 8.1 on-the-go (otg) controller the otg controller provides all the control, monitoring and switching functions required in otg operations. 8.2 advanced philips slave host controller (pshc) the advanced philips slave hc is designed for highly optimized usb host functionality. many advanced features are integrated to fully utilize the usb bandwidth. a number of tasks are performed at the hardware level. this reduces the requirement on the microprocessor and thus speeds up the system. 8.3 philips device controller (dc) the philips dc is a high performance usb device with up to 14 programmable endpoints. these endpoints can be con gured as double-buffered endpoints to further enhance the throughput. 8.4 phase-locked loop (pll) clock multiplier a 12 mhz-to-48 mhz clock multiplier pll is integrated on-chip. this allows the use of a low-cost 12 mhz crystal that also minimizes electro-magnetic interference (emi) because of low frequency. no external components are required for the operation of pll. 8.5 usb and otg transceivers the integrated transceivers (for typical downstream port) directly interface to the usb connectors (type a) and cables through some termination resistors. the transceiver is compliant with universal serial bus speci cation rev 2.0 . 8.6 overcurrent protection the isp1362 has a built-in overcurrent protection circuitry. this feature monitors the current drawn on the downstream v bus and switches off v bus when the current exceeds the current threshold. the built-in overcurrent protection feature can be used when the port acts as a host port. 8.7 bus interface the bus interface connects the microprocessor to the usb host and the usb device allowing fast and easy access to both. 8.8 dc and hc buffer memory 4096 bytes (host) and 2462 bytes (device) of built-in memory provide suf cient space for the buffering of usb traf c. memory in the hc is addressable by using the fast and versatile direct addressing method.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 14 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.9 goodlink indication of a good usb connection is provided through the goodlink technology (open-drain, maximum current: 4 ma). during enumeration, led indicators blink on momentarily corresponding to the enumeration traf c of the isp1362 ports. the led also blinks on whenever there is valid traf c to the usb ports. in the suspend mode, the led is off. this feature of goodlink provides a user-friendly indication on the status of the usb traf c between the host and the hub, as well as the connected devices. it is a useful diagnostics tool to isolate faulty equipment and helps to reduce eld support and hotline costs. 8.10 charge pump the charge pump generates a 5 v supply from 3.3 v to drive v bus when the isp1362 is an a-device in the otg mode. for details, see section 11.6 . 9. host and device bus interface the interface between the external microprocessor and the isp1362 host controller (hc) and device controller (dc) is separately handled by the individual bus interface circuitry. the host or device automux selects the path for the host access or the device access. this selection is determined by the a1 address line. for any access to hc or dc registers, the command phase and the data phase are needed, which is determined by the a0 address line. all the functionality of the isp1362 can be accessed using a group of registers and two buffer memory areas (one for the hc and the other the dc). registers can be accessed using the programmed i/o (pio) mode. the buffer memory can be accessed using both the pio and direct memory access (dma) modes. when cs is low (active), the address pin a1 has priority over dreq and d a ck. therefore, as long as the cs pin is held low, the isp1362 bus interface does not respond to any d a c k signals. when cs is high (inactive), the bus interface will respond to dreqn and d a ckn. the address pin a1 will be ignored when cs is inactive. an active d a ck n signal when the dreqn is inactive will be ignored. if dreq1, d a ck1, dreq2 and d a ck2 are active, the bus interface will be switched off to avoid potential data corruption. ta b l e 3 provides the bus access priority for the isp1362. [1] only for enabling of the bus and disabling of the bus. depends only on the d a ck signal. table 3: bus access priority table for the isp1362 priority cs a1 d a ck1 d a ck2 dreq1 dreq2 hc and dc active 1llxxxxhc 2 l hxxxxdc 3hxlxhlhc [1] 4hxxllhdc [1] 5 h x x x h h no driving
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 15 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.1 memory organization the buffer memory in the hc uses a multicon gurable direct addressing architecture. the 4096 bytes hc buffer memory is shared by the istl0, istl1, intl and atl buffers. istl0 and istl1 are used for isochronous traf c (double buffer), intl is used for interrupt traf c, and atl is used for control and bulk traf c. the allocation of the buffer memory follows the sequence istl0, istl1, intl, atl and unused memory. for example, consider that the buffer sizes of the istl, intl and atl buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. then, istl0 will start from memory location 0, istl1 will start from memory location 1024 (size of istl0), intl will start from memory location 2048 (size of istl0 + size of istl1) and atl will start from memory location 3072 (size of istl0 + size of istl1 + size of intl). the hcd has the responsibility to ensure that the sum of the four memory buffers does not exceed the total memory size. if this condition is violated, it will lead to data corruption. the buffer size must be a multiple of two bytes (one word). the buffer memory of the dc follows a similar architecture. details on the dc memory area allocation can be found in section 13.3 . note that the dc buffer memory does not support the direct addressing mode. 9.1.1 memory organization for the hc the hc in the isp1362 has a total of 4096 bytes of buffer memory. this buffer area is divided into four parts (see ta b l e 4 and figure 4 ): the istl0 and istl1 buffers must have the same size. memory is allocated by the hc according to the value set by the hcd in hcistlbuffersize, hcintlbuffersize and hcatlbuffersize. all buffer sizes must be multiples of two bytes (one word). table 4: buffer memory areas and their applications buffer memory area application istl0 and istl1 isochronous transfer (double buffering) intl interrupt transfer atl control and bulk transfer
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 16 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the intl and atl buffers use blocked memory management scheme to enhance the status and control capability of each and every individual ptd structure. the intl and atl buffers are further divided into blocks of equal sizes depending on the value written to the hcatlblksize register (atl) and the hcintlblksize register (intl). the isp1362 hc supports up to 32 blocks in the atl and intl buffers. each of these blocks can be used for one complete philips transfer descriptor (ptd) data. note that the block size does not include the 8-byte ptd header and is strictly the size of the payload. both the atl and intl block sizes must be a multiple of dword (4 bytes). fig 4. recommended values of the isp1362 buffer memory allocation. 004aaa053 istl0 area (512 bytes) istl1 area (512 bytes) 0x0fff intl area (512 bytes) atl area (1536 bytes) 0x0a00 0x09ff 0x0800 0x07ff 0x0400 0x03ff 0x0000
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 17 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. figure 5 provides a snapshot of a sample atl or intl buffer area of 256 bytes with a block size of 64 bytes. the hcd may put a ptd with payload size of up to 64 bytes but not more. depending on the atl or intl buffer size, up to 32 atl blocks and 32 intl blocks can be allocated. note that a portion of the atl or intl buffer remains unused. this is allowed but can be avoided by choosing the appropriate atl or intl buffer size and block size. the istl0 or istl1 buffer memory (for isochronous transfer) uses a different memory management scheme (see figure 6 ). there is no xed block size for the istl buffer memory. while the ptd header remains 8 bytes for all ptds, the ptd payload can be of any size. the ptd payload, however, is padded to the next dword boundary when the hc calculates the location of the next ptd header. the isp1362 hc checks the payload size from the total size eld of the ptd itself and calculates the location of the next ptd header based on this information. fig 5. a sample snapshot of the atl or intl memory management scheme. 004aaa055 8 bytes ptd header 64 bytes ptd header 8 bytes ptd header payload area 64 bytes ptd header payload area 8 bytes ptd header 64 bytes ptd header payload area block of 72 bytes (64 + 8, where 64 is the block size defined) 72 bytes 72 bytes starting address of the atl or intl buffer area
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 18 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.1.2 memory organization for the dc the isp1362 dc has a total of 2462 bytes of built-in buffer memory. this buffer memory is multicon gurable to support the requirements of different applications. the dc buffer memory is divided into 16 areas to be used by control out, control in and 14 programmable endpoints. figure 7 provides a snapshot of the dc buffer memory. total size is a 10-bit eld in the ptd. fig 6. a sample snapshot of the istl memory management scheme. 004aaa054 ptd header (total size = 64) ptd payload (64 bytes) ptd header (total size = 160) ptd payload (160 bytes) ptd header (total size = 32) ptd payload (32 bytes) 72 bytes (64 + 8) 168 bytes (160 + 8) 40 bytes (32 + 8) starting address of istl0 or istl1
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 19 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the buffer memory is con gured by the dcendpointcon guration registers (ecrs). although the control endpoint has a xed con guration, all 16 endpoints (control out, control in and 14 programmable endpoints) must be con gured before the dc internally allocates the buffer. the 14 programmable endpoints could be programmed into sizes ranging from 16 bytes to 1023 bytes, single or double buffering. the dc buffer memory for each endpoint can be accessed through the dcreadendpointbuffer and dcwriteendpointbuffer registers. 9.2 pio access mode the isp1362 provides the pio mode for external microprocessors to access its internal control registers and buffer memory. it occupies only four i/o ports or four memory locations of a microprocessor. an external microprocessor can read or write to the internal control registers and buffer memory of the isp1362 through the pio operating mode. figure 8 shows the pio interface between a microprocessor and the isp1362. fig 7. dc buffer memory organization. 004aaa057 control out (64 bytes) endpoint 1 (128 bytes) endpoint 2 (128 bytes) endpoint 3 (512 bytes) endpoint 4 (64 bytes) control in (64 bytes) endpoint 5 (64 bytes) endpoint 6 (96 bytes) endpoint 7 (96 bytes)
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 20 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3 dma mode the isp1362 also provides the dma mode for external microprocessors to access the internal buffer memory of the isp1362. the dma operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the isp1362. remark: the dma operation must be controlled by the dma controller of the external microprocessor system (master). figure 9 shows the dma interface between a microprocessor system and the isp1362. the isp1362 provides two dma channels. the dma channel 1 (controlled by the dreq1 and d a ck1 signals) is for the dma transfer between the system memory of a microprocessor and the internal buffer memory of the isp1362 hc. the dma channel 2 (controlled by the dreq2 and d a ck2 signals) is for the dma transfer between the system memory of a microprocessor and the internal buffer memory of the isp1362 dc. the isp1362 provides an internal end-of-transfer (eot) signal to terminate the dma transfer. fig 8. pio interface between a microprocessor and the isp1362. 004aaa042 d [ 15:0 ] rd wr cs a2 irq2 micro- processor isp1362 d [ 15:0 ] p bus interface rd wr cs a1 a1 irq1 a0 int1 int2 fig 9. dma interface between a microprocessor and the isp1362. 004aaa043 d [ 15:0 ] rd wr dack1 dreq1 micro- processor isp1362 d [ 15:0 ] p bus interface rd wr dack1 dreq1 dack2 dreq2 dack2 dreq2
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 21 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 pio access to internal control registers ta b l e 5 shows the i/o port addressing in the isp1362. the complete i/o port address decoding should combine with the chip select signal ( cs) and the address lines (a1 and a0). the direction of access of i/o ports, however, is controlled by the rd and wr signals when rd is low, the microprocessor reads data from the data port of the isp1362 (see figure 10 ). when wr is low, the microprocessor writes command to the command port or writes data to the data port (see figure 11 ). the register structure in the isp1362 is a command-data register pair structure. a complete register access needs a command phase followed by a data phase. the command (also named as the index of a register) is used to inform the isp1362 about the register that will be accessed at the data phase. on the 16-bit data bus of a microprocessor, a command occupies the lower byte and the upper byte is lled with zeros (see figure 12 ). for 32-bit registers, the access cycle is shown in figure 13 . it consists of a command phase followed by two data phases. table 5: i/o port addressing cs a1 a0 access data bus width description l l l r/w 16 bits hc data port l l h w 16 bits hc command port l h l r/w 16 bits dc data port l h h w 16 bits dc command port when a1 = l, microprocessor accesses the hc. when a1 = h, microprocessor accesses the dc. fig 10. microprocessor access to the hc or the dc. 004aaa122 p bus interface host bus interface device bus interface bus interface a1 0 1
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 22 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. when a0 = l, microprocessor accesses the data port. when a0 = h, microprocessor accesses the command port. fig 11. access to internal control registers. fig 12. pio register access. 004aaa160 cmd/data switch commands control registers command register data port a0 command port . . . host or device bus interface 1 0 004aaa045 read 16-bit write16-bit a0/a1 d[15:0] rd cs a0/a1 d[15:0] wr cs
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 23 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 13. pio access for a 16 or 32-bit register. 004aaa046 a0/a1 d[15:0] rd cs wr a0/a1 d[15:0] rd cs wr reading from a 16/32-bit register 16-bit access 32-bit access command phase data phase second data phase for 32-bit register writing to a 16/32-bit register 16-bit access 32-bit access command phase data phase second data phase for 32-bit register
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 24 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following is a sample code for pio access to internal control registers: unsigned long read_reg32(unsigned char reg_no) { unsigned int result_l,result_h; unsigned long result; outport(hc_com, reg_no); // command phase result_l=inport(hc_data); // data phase result_h=inport(hc_data); // data phase result = result_h; result = result<<16; result = result+result_l; return(result); } void write_reg32(unsigned char reg_no, unsigned long data2write) { unsigned int low_word; unsigned int hi_word; low_word=data2write&0x0000ffff; hi_word=(data2write&0xffff0000)>>16; outport(hc_com,reg_no|0x80); // command phase outport(hc_data,low_word); // data phase outport(hc_data,hi_word); // data phase } unsigned int read_reg16(unsigned char reg_no) { unsigned int result; outport(hc_com, reg_no); // command phase result=inport(hc_data); // data phase return(result); } void write_reg16(unsigned char reg_no, unsigned int data2write) { outport(hc_com,reg_no|0x80); // command phase outport(hc_data,data2write); // data phase } 9.5 pio access to the buffer memory the buffer memory in the isp1362 can be addressed using either the direct addressing method or the indirect addressing method. 9.5.1 pio access to the buffer memory by using direct addressing this method uses the hcdirectaddresslength register to specify two parameters required to randomly access the isp1362 buffer memory (total of 4096 bytes). these two parameters are:
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 25 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. starting address location to start writing or reading data length number of bytes to write or read. the following is a sample code for setting the hcdirectaddresslength register: void set_diraddrlen(unsigned int data_length,unsigned int addr) { unsigned long regdata = 0; regdata =(long)(addr&0x7fff); regdata|=(((long)data_length)<<16); write_reg32(hcdiraddrlen,regdata); } after the proper value is written to the hcdirectaddresslength register, data is accessible from the hcdirectaddressdata register (called as hcdiraddr_port in the following sample code). a sample code for writing word_size bytes of data from *w_ptr to the memory locations of the isp1362 buffer starting from the address start_addr is as follows: void direct_write(unsigned int *w_ptr,unsigned int start_addr,unsigned int word_size) { unsigned int cnt=0; set_diraddrlen(word_size*2,start_addr); outport(hc_com,hcdiraddr_port|0x80); // hc_com is system address of // hc command port do { outport(hc_data,*(w_ptr+cnt)); // hc_data is system address of // hc data port cnt++; } while(cnt philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 26 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. write_reg16(hctransfercnt,word_size*2); outport(hc_com,hcatl_port|0x80); // hc_com is system address of hc // command port cnt=0; do { outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of hc // data port cnt++; } while(cnt<(word_size)); remark: the hctransfercounter register counts the number of bytes even though the transfer is in number of words. therefore, the transfer counter should be set to word_size 2. incorrect setting of the hctransfercounter register may cause the isp1362 to go into an indeterminate state. the buffer memory access using indirect addressing always starts from the location 0 of each buffer area. only the front portion of the memory (example: rst 64 bytes of a 1024 bytes buffer) can be accessed. therefore, to access a portion of the memory that does not start from memory location 0, all memory locations before that location must be accessed in a sequential order. the method is similar to the sequential le access method. 9.6 setting up a dma transfer the isp1362 uses two dma channels to individually serve the hc and the dc. the dma transfer allows the system cpu to work on other tasks while the dma controller transfers data to or from the isp1362. the dma slave controller, in the isp1362, is compatible with the 8327 type dma controller. the dma transfer can be used with the direct addressing mode or the indirect addressing mode. the registers used in these two modes are shown in ta b l e 6 . [1] in the direct addressing mode, hctransfercounter must be set to 0001h. 9.6.1 con guring registers for a dma transfer to set up a dma transfer, the following hc registers must be con gured depending on the type of transfer required: hchardwarecon guration dreq1 output polarity (bit 5) d a ck1 input polarity (bit 6) d a ck mode (bit 8). hc pinterruptenable if you want an interrupt to be generated after the dma transfer is complete, set eotinterruptenable (bit 3). table 6: registers used in addressing modes addressing mode [1] hcdmacon guration bit[3:1] total bytes to transfer direct addressing 1xxb hcdirectaddresslength indirect addressing 0xxb hctransfercounter
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 27 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. hc pinterrupt before initiating the dma transfer, clear alleotinterrupt (bit 3). this bit is set when the dma transfer is complete. hctransfercounter if dmacounterenable of the hcdmacon guration register is set (that is, the dma counter is enabled), hctransfercounter must be set to the number of bytes to be transferred. hcdmacon guration read or write dma (bit 0) targeted buffer : istl0, istl1, atl and intl (bits 1 to 3) dma enable or disable (bit 4) burst length (bits 5 to 6) dma counter enable (bit 7). remark: con gure the hcdmacon guration register only after you have con gured all the other registers. the isp1362 will assert dreq1 once the dma enable bit in this register is set. 9.6.2 combining the two dma channels the isp1362 allows systems with limited dma channels to use a single dma channel (dma1) for both the hc and the dc. this option can be enabled by writing logic 1 to the onedma bit of the hchardwarecon guration register. if this option is enabled, the polarity of the dc dma and the hc dma must be set to dack active low and dreq active high. 9.7 interrupts various events in the hc, the dc and the otg controller can be programmed to generate a hardware interrupt. by default, the interrupt generated by the hc and the otg controller is routed out at the int1 pin and the interrupt generated by the dc is routed out at the int2 pin. 9.7.1 interrupt in the hc and the otg controller there are two levels of interrupts represented by level 1 and level 2 (see figure 14 ).
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 28 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 14. hc and otg interrupt logic. istl_1_int 004aaa395 latch oneint interruptpinenable fno rhsc mie ue rd sf so rhsc fno ue rd sf so or or otg_irq_interruptenable atl_irq_interruptenable intl_irq_interruptenable clkready hcsuspendedenable oprinterruptenable eot_interruptenable istl_1_interruptenable istl_0_interruptenable sofinterruptenable otg_irq atl_irq intl_irq clkready hcsuspended opr_reg aiieotinterrupt istl_0_int sof_int from int2 le hchardwareconfiguration register hchardwareconfiguration register int1 level 1 hcpinterrupt register hcinterruptenable register hcinterruptstatus register hcpinterruptenable register otginterrupt register a_vbus_vld_c b_sess_end_c a_sess_vld_c b_sess_vld_c rmt_conn_c otg_suspnd otg_resume a_srp_det b_se0_srp otg_tmr_timeout id_reg_c otginterruptenable register a_vbus_vld_ie b_sess_end_ie a_sess_vld_ie b_sess_vld_ie rmt_conn_ie otg_suspnd_ie otg_resume_ie a_srp_det_ie b_se0_srp_ie otg_tmr_ie id_reg_ie or level 2 (otg group) level 2 (opr group)
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 29 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the interrupt level 2 (opr group) contains six possible interrupt events (recorded in the hcinterruptstatus register). when any of these events occurs, the corresponding bit would be set to logic 1, and if the corresponding bit in the hcinterruptenable register is also logic 1, the 6-input or gate would output logic 1. this output is combined with the value of mie (bit 31 of hcinterruptenable) using the and operation and logic 1 output at this and gate will cause the opr bit in the hc pinterrupt register to be set to logic 1. the interrupt level 2 (otg group) contains 11 possible interrupt events (recorded in the otginterrupt register). when any of these events occurs, the corresponding bit would be set to logic 1, and if the corresponding bit in the otginterruptenable register is also logic 1, the 11-input or gate would output logic 1 and cause the otg_irq bit in the hc pinterrupt register to be set to logic 1. the level 1 interrupts contains 10 possible interrupt events. the hc pinterrupt and hc pinterruptenable registers work in the same way as the hcinterruptstatus and hcinterruptenable registers. the output from the 10-input or gate is connected to a latch, which is controlled by interruptpinenable (the bit 0 of hchardwarecon guration register). when the software wishes to temporarily disable the interrupt output of the isp1362 hc and otgc, follow this procedure: 1. set the interruptpinenable bit in hchardwarecon guration register to logic 1. 2. clear all bits in the hc pinterrupt register. 3. set the interruptpinenable bit to logic 0. to re-enable the interrupt generation, set the interruptpinenable bit to logic 1. remark: the interruptpinenable bit in the hchardwarecon guration register controls the latch of the interrupt output. when this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operation on the interrupt control registers. if int1 is asserted, and the hcd wishes to temporarily mask off the int signal without clearing the hc pinterrupt register, follow this procedure: 1. make sure that the interruptpinenable bit is set to logic 1. 2. clear all bits in the hc pinterruptenable register. 3. set the interruptpinenable bit to logic 0. to re-enable the interrupt generation: 1. set all bits in the hc pinterruptenable register according to the hcd requirements. 2. set the interruptpinenable bit to logic 1. 9.7.2 interrupt in the dc the registers that control the interrupt generation in the isp1362 dc are: dcmode (bit 3) dchardwarecon guration (bits 0 and 1)
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 30 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. dcinterruptenable dcinterrupt. the dcmode register (bit 3) is the overall dc interrupt enable. dchardwarecon guration determines the following features: level-triggered or edge-triggered (bit 1) output polarity (bit 0). for details on the interrupt logic in the dc, refer to the interrupt control application note. 9.7.3 combining int1 and int2 in some embedded systems, interrupt inputs to the cpu are a very scarce resource. the system designer might want to use just one interrupt line to serve the hc, the dc and the otg controller. in such a case, make sure the oneint feature is activated. when oneint (bit 9 of the hchardwarecon guration register) is set to logic 1, both the int1 (hc or otg controller) interrupt and the int2 (dc) interrupt are routed to pin int1, thereby reducing hardware resource requirements. remark: both the host controller (or otg controller) and the device controller interrupts must be set to the same polarity (active high or active low) and the same trigger type (edge or level). failure to conform to this will lead to unpredictable behavior of the isp1362. 9.7.4 behavior difference between level-triggered and edge-triggered interrupts in many microprocessor systems, the operating system disables an interrupt when it is in an interrupt service routine (isr). if there is an interrupt event during this period, it will lead to: level-triggered interrupt: when the isp1362 interrupt asserts, the operating system takes no action because it disables the interrupt when it is in the isr. the interrupt line of the isp1362 remains asserted. when the operating system exits the isr and re-enables the interrupt processing, it sees the asserted interrupt line and immediately enters the isr. edge-triggered interrupt: when the isp1362 outputs a pulse, the operating system takes no action because it disables the interrupt when it is in the isr. the interrupt line of the isp1362 goes back to the inactive state. when the operating system exits the isr and re-enables the interrupt processing, it sees no pending interrupt. as a result, the interrupt is missed. if the system needs to know whether an interrupt (approximately 160 ns pulse width) occurs during this period, it may read the hc pinterrupt register (see ta b l e 6 8 ). 10. power-on reset (por) when v cc is directly connected to the reset pin, the internal por pulse width (t porp ) will be typically 800 ns. the pulse is started when v cc rises above v trip (2.03 v).
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 31 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. to give a better view of the functionality, figure 15 shows a possible curve of v cc with dips at t2 t3 and t4 t5. if the dip at t4 t5 is too short (that is, < 11 s), the internal por pulse will not react and will remain low. the internal por starts with a high at t0. at t1, the detector will see the passing of the trip level and a delay element will add another t porp before it drops to low. the internal por pulse will be generated whenever v cc drops below v trip for more than 11 s. the reset pin can be either connected to v cc (using the internal por circuit) or externally controlled (by the micro, asic, and so on). figure 16 shows the availability of the clock with respect to the external reset pulse. 11. on-the-go (otg) controller 11.1 introduction otg is a supplement to the hi-speed usb (usb 2.0) speci cation that augments existing usb peripherals by adding to these peripherals limited host capability to support other targeted usb peripherals. it is primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. non-portable devices (even standard hosts), nevertheless, can also bene t from otg features. (1) porp = power-on reset pulse. fig 15. internal power-on reset timing. stable external clock is available at a. fig 16. clock with respect to the external power-on reset. 004aaa482 v cc t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp reset external clock a 004aaa484
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 32 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the isp1362 otg controller is designed to perform all the tasks speci ed in the otg supplement. it supports host negotiation protocol (hnp) and session request protocol (srp) for dual-role devices. the isp1362 uses software implementation of hnp and srp for maximum exibility. a set of otg registers provides the control and status monitoring capabilities to support software hnp or srp. besides the normal usb transceiver, timers and analog components required by otg are also integrated on-chip. the analog components include: built-in 3.3 v-to-5 v charge pump voltage comparators pull-up or pull-down resistors on data lines charge or discharge resistors for v bus . 11.2 dual-role device when port 1 of the isp1362 is con gured in the otg mode, it can be used as an otg dual-role device. a dual-role device is a usb device that can function either as a host or as a peripheral. as a host, the isp1362 can support all four types of transfers (control, bulk, isochronous and interrupt) at full-speed or low-speed. as a peripheral, the isp1362 can support two control endpoints and up to 14 con gurable endpoints, which can be programmed to any of the four transfer types. the default role of the isp1362 is controlled by the id pin, which in turn is controlled by the type of plug connected to the mini-ab receptacle. if id = low (mini-a plug connected), it becomes an a-device, which is a host by default. if id = high (mini-b plug connected), it becomes a b-device, which is a peripheral by default. both the a-device and the b-device work on a session base. a session is de ned as the period of time in which devices exchange data. a session starts when v bus is driven and ends when v bus is turned off. both the a-device and the b-device may start a session. during a session, the role of the host can be transferred back and forth between the a-device and the b-device any number of times by using hnp. if the a-device wants to start a session, it turns on v bus by enabling the charge pump. the b-device detects that v bus has risen above the b_sess_vld level and assumes the role of a peripheral asserting its pull-up resistor on the dp line. the a-device detects the remote pull-up resistor and assumes the role of a host. then, the a-device can communicate with the b-device as long as it wishes. when the a-device nishes communicating with the b-device, the a-device turns-off v bus and both the devices nally go into the idle state. see figure 18 and figure 19 . if the b-device wants to start a session, it must initiate srp by data line pulsing and v bus pulsing . when the a-device detects any of these srp events, it turns on its v bus (note that only the a-device is allowed to drive v bus ). the b-device assumes the role of a peripheral, and the a-device assumes the role of a host. the a-device detects that the b-device can support hnp by getting the otg descriptor from the b-device. the a-device will then enable the hnp hand-off by using setfeature (b_hnp_enable) and then go into the suspend state. the b-device signals claiming the host role by deasserting its pull-up resistor. the a-device acknowledges by going into the peripheral state. the b-device then assumes the role of a host and
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 33 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. communicates with the a-device as long as it wishes. when the b-device nishes communicating with the a-device, both the devices nally go into the idle state. see figure 18 and figure 19 . 11.3 session request protocol (srp) as a dual-role device, the isp1362 can initiate and respond to srp. the b-device initiates srp by data line pulsing followed by v bus pulsing. the a-device can detect either data line pulsing or v bus pulsing. 11.3.1 b-device initiating srp the isp1362 can initiate srp by performing the following steps: 1. detect initial conditions [read id_reg, b_sess_end and se0_2ms (bits 0, 2 and 9) of the otgstatus register]. 2. start data line pulsing [set loc_conn (bit 4) of otgcontrol register to logic 1]. 3. wait for 5 ms to 10 ms. 4. stop data line pulsing [set loc_conn (bit 4) of otgcontrol register to logic 0]. 5. start v bus pulsing [set chrg_v bus (bit 1) of the otgcontrol register to logic 1]. 6. wait for 10 ms to 20 ms. 7. stop v bus pulsing [set chrg_v bus (bit 1) of the otgcontrol register to logic 0]. 8. discharge v bus for about 30 ms [by using dischrg_v bus (bit 2) of the otgcontrol register], optional. the b-device must complete both data line pulsing and v bus pulsing within 100 ms. 11.3.2 a-device responding to srp the a-device must be able to respond to one of the two srp events: data line pulsing or v bus pulsing. the isp1362 allows you to choose which srp to support and has a mechanism to disable or enable the srp detection. this is useful for some applications under certain cases. for example, if the a-device battery is low, it may not want to turn on its v bus by detecting srp. in this case, it may choose to disable the srp detection function. when the data line srp detection is used, the isp1362 can detect either the dp pulsing or the dm pulsing. this means a peripheral-only device can initiate data line pulsing srp through dp (full-speed) or dm (low-speed). a dual-role device will always initiate data line pulsing srp through dp because it is a full-speed device. steps to enable the srp detection by v bus pulsing: set a_sel_srp (bit 9) of the otgcontrol register to logic 0. set a_srp_det_en (bit 10) of the otgcontrol register to logic 1. steps to enable the srp detection by data line pulsing: set a_sel_srp (bit 9) of the otgcontrol register to logic 1. set a_srp_det_en (bit 10) of the otgcontrol register to logic 1. steps to disable the srp detection: set a_srp_det_en (bit 10) of the otgcontrol register to logic 0.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 34 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.4 host negotiation protocol (hnp) hnp is used to transfer control of the host role between the default host (a-device) and the default peripheral (b-device) during a session. when the a-device is ready to give up its role as a host, it will condition the b-device by setfeature (b_hnp_enable) and will go into suspend . if the b-device wants to use the bus at that time, it signals a disconnect to the a-device. then, the a-device will take the role of a peripheral and the b-device will take the role of a host. 11.4.1 sequence of hnp events the sequence of events for hnp as observed on the usb bus is illustrated in figure 17 . as can be seen in figure 17 : 1. the a-device completes using the bus and stops all bus activity (that is, suspends the bus). 2. the b-device detects that the bus is idle for more than 5 ms and begins hnp by turning off the pull-up on dp. this allows the bus to discharge to the se0 state. 3. the a-device detects se0 on the bus and recognizes this as a request from the b-device to become a host. the a-device responds by turning on its dp pull-up within 3 ms of rst detecting se0 on the bus. 4. after waiting for 30 s to ensure that the dp line is not high because of the residual effect of the b-device pull-up, the b-device notices that the dp line is high and the dm line is low (that is, j state). this indicates that the a-device has recognized the hnp request from the b-device. at this point, the b-device becomes a host and asserts bus reset to start using the bus. the b-device must assert the bus reset (that is, se0) within 1 ms of the time that the a-device turns on its pull-up. 5. when the b-device completes using the bus, it stops all bus activity. optionally, the b-device may turn on its dp pull-up at this time. fig 17. hnp sequence of events. a-device 1 5 7 2 3 4 6 8 b-device 004aaa079 dp composite legend dp driven pull-up dominates pull-down dominates normal bus activity
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 35 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. the a-device detects lack of bus activity for more than 3 ms and turns off its dp pull-up. alternatively, if the a-device has no further need to communicate with the b-device, the a-device may turn off v bus and end the session. 7. the b-device turns on its pull-up. 8. after waiting 30 s to ensure that the dp line is not high because of the residual effect of the a-device pull-up, the a-device notices that the dp-line is high (and the dm line is low) indicating that the b-device is signaling a connect and is ready to respond as a peripheral. at this point, the a-device becomes a host and asserts the bus reset to start using the bus. 11.4.2 otg state diagrams figure 18 and figure 19 show the state diagrams for the dual-role a-device and the dual-role b-device, respectively. for a detailed explanation, refer to on-the-go supplement to the usb 2.0 speci cation rev. 1.0a . the otg state machine is implemented with software. the inputs to the state machine come from four sources: hardware signals from the usb bus, software signals from the application program, internal variables with the state machines and timers: hardware inputs: include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end, a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume, a_srp_det and b_se0_srp. all these inputs can be derived from the otginterrupt and otgstatus registers. software inputs: include a_bus_req, a_bus_drop and b_bus_req. internal variables: include a_set_b_hnp_en, b_hnp_enable and b_srp_done. timers: the hnp state machine uses four timers: a_wait_vrise_tmr, a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. all timers are started on entry to and reset on exit from their associated states. the isp1362 provides a programmable timer that can be used as any of these four timers.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 36 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 18. dual-role a-device state diagram. 004aaa077 a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ a_vbus_err drv_vbus/ loc_conn/ loc_sof/ a_wait_vrise drv_vbus loc_conn/ loc_sof/ a_wait_bcon drv_vbus loc_conn/ loc_sof/ a_host drv_vbus loc_conn/ loc_sof a_wait_vfall drv_vbus/ loc_conn/ loc_sof/ a_peripheral drv_vbus loc_conn loc_sof/ a_suspend drv_vbus loc_conn/ loc_sof/ b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id start a_bus_drop/ & (a_bus_req | a_srp_det) id | a_bus_req | (a_sess_vld/ & b_conn/) a_bus_req | b_bus_resume a_bus_req/ | a_suspend_req a_vbus_vld/ a_vbus_vld/ a_vbus_vld/ b_conn a_vbus_vld/ id | a_bus_drop b_bus_suspend id | a_bus_drop | a_vbus_vld | a_wait_vrise_tmout id | a_bus_drop | a_wait_bcon_tmout id | b_conn/ | a_bus_drop b_conn/ & a_set_b_hnp_en b_conn/ & a_set_b_hnp_en/ id | a_bus_drop | a_aidl_bdis_tmout id | a_bus_drop
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 37 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.4.3 hnp implementation and otg state machine the otg state machine is the software behind all the otg functionality. it is implemented in the microprocessor system that is connected to the isp1362. the isp1362 provides all input status, the output control and timers to fully support the state machine transitions in figure 18 and figure 19 . these registers include: otgcontrol register: provides control to v bus driving, charging or discharging, data line pull-up or pull-down, srp detection, and so on otgstatus register: provides status detection on v bus and data lines including id, v bus session valid, session end, overcurrent, bus status otginterrupt register: provides interrupts for status change in otgstatus register bits and the otgtimer time-out event otginterruptenable register: provides interrupt mask for otginterrupt register bits otgtimer register: provides 0.01 ms base programmable timer for use in the otg state machine. the otg interrupt is generated on the int1 pin. it is shared with the hc interrupt. to enable the otg interrupt, perform these steps: 1. set the polarity and the level-triggering or edge-triggering mode of the hchardwarecon guration register (bits 1 and 2, default is level-triggered, active low). fig 19. dual-role b-device state diagram. 004aaa078 b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ b_srp_init pulse loc_conn pulse chrg_vbus loc_sof/ b_peripheral chrg_vbus/ loc_conn loc_sof/ b_host chrg_vbus/ loc_conn/ loc_sof b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id/ start b_bus_req/ | a_conn/ b_sess_vld id/ | b_sess_vld/ id/ | b_sess_vld/ id/ | b_sess_vld/ a_bus_resume | b_ase0_brst_tmout b_bus_req & b_hnp_en & a_bus_suspend a_conn b_bus_req & b_sess_end & b_se0_srp id/ | b_srp_done
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 38 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. set the corresponding bits of the otginterruptenable register (bits 0 to 8, or some of them). 3. set bit otg_irq_interruptenable of the hc pinterruptenable register (bit 9). 4. set bit interruptpinenable of the hchardwarecon guration register (bit 0). when an interrupt is generated on int1, perform these steps in the interrupt service routine to get the related otg status: 1. read the hc pinterrupt register. if otg_irq (bit 9) is set, then step 2. 2. read the otginterrupt register. if any of the bits 0 to 4 are set, then step 3. 3. read the otgstatus register. the otg state machine routines are called when any of the inputs is changed. these inputs come from either otg registers (hardware) or application program (software). the outputs of the state machine include control signals to the otg register (for hardware) and states or error codes (for software). for more information, refer to the philips document isp136x embedded programming guide . 11.5 power saving in the idle state and during wake-up the isp1362 can be put in the power saving mode if the otg device is not in a session. this signi cantly reduces the power consumption. in this mode, both the dc and the hc are suspended. the pll and the oscillator are stopped, and the charge pump is in the suspend state. as an otg device, however, the isp1362 is required to respond to the srp event. to support this, a lazyclock is kept running when the chip is in the power saving mode. an srp event will wake up the chip (that is, enable the pll and the oscillator). besides this, an id change or b_sess_vld detection can also wake up the chip. these wake-up events can be enabled or disabled by programming the related bits of the otginterruptenable register before putting the chip in the power saving mode. if the bit is set, then the corresponding event (status change) will wake up the isp1362. if the bit is cleared, then the corresponding event will not wake up the isp1362. you can also wake up the isp1362 from the power saving mode by using software. this is accomplished by accessing any of isp1362 registers. accessing a register will assert cs of the isp1362, and therefore, set it awake. 11.6 current capacity of the otg charge pump the isp1362 uses a built-in charge pump to generate a 5 v v bus supply from a 3.3 v 0.3 v voltage source. the only external component required is a capacitor. the value of this capacitor depends on the amount of current drive required. ta b l e 7 provides two recommended capacitor values and the corresponding current drive. table 7: recommended capacitor values capacitance v cc current 27 nf 3.0 v to 3.6 v 8 ma 82 nf 3.0 v to 3.3 v 14 ma 3.3 v to 3.6 v 20 ma
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 39 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the connection of the external capacitor (c ext ) is given in the partial schematics in figure 20 . remark: if the internal charge pump is not used, c ext is not required. 12. usb host controller (hc) 12.1 usb states of the hc the usb hc in the isp1362 has four usb states: usboperational, usbreset, usbsuspend and usbresume . these states de ne the responsibilities of the hc related to the usb signaling and bus states. these signals are visible to the hc driver (hcd), the software driver of the hc, by using the control registers of the isp1362 usb hc. fig 20. external capacitors connection. 004aaa154 isp1362 v bus cp_cap2 cp_cap1 c ext otg v bus 4.7 f 0.1 f fig 21. usb hc states of the isp1362. mgt947 usboperational usbsuspend usbresume usbresume write or remote wake-up usbreset usboperational write usboperational write usbsuspend write usbreset write usbreset write usbreset write hardware or software reset
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 40 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the usb states are re ected in the hostcontrollerfunctionalstate (hcfs) eld of the hccontrol register. the hcd is allowed to perform only the usb state transitions shown in figure 21 . 12.2 usb traf c generation usb traf c can be generated only when the isp1362 usb hc is under the usboperational state. therefore, the hcd must set the isp1362 usb hc into the usboperational state. this is done by setting the hcfs eld of the hccontrol register before generating usb traf c. a brief ow of usb traf c generation is described as follows: 1. reset the isp1362 by using the reset pin or the software reset. 2. set the physical size of the atl, interrupt, istl0 and istl1 buffers. 3. write the 32-bit hexadecimal value 0x800000fd to the hcinterruptenable register. this will enable all the interrupt events in the register to trigger the hardware interrupt (see section 15.1.5 ). 4. write the 16-bit hexadecimal value 0x002d to the hchardwarecon guration register. this will set up the hc to level triggered and active high interrupt setting (see section 15.4.1 ). 5. write 0x05000b02 to hcrhdescriptora and 0x00000000 to hcrhdescriptorb. 6. write the 16-bit hexadecimal value 0x0680 to the hccontrol register to set the isp1362 into the operation mode (see section 15.1.2 ). 7. read the hcrhportstatus[1] and hcrhportstatus[2] registers. these registers contain the 32-bit hexadecimal value 0x00010100 (see section 15.3.4 ). 8. connect a full-speed device to one of the downstream ports or use a 1.5 k ? resistor to pull up the dp line (to emulate a full-speed device). 9. read the hcrhportstatus[1] and hcrhportstatus[2] registers. the hexadecimal value of one of the registers must change to 0x00010101 indicating that a device connection has been detected. 10. write the 32-bit hexadecimal value 0x00000102 into either hcrhportstatus[1] or hcrhportstatus[2] depending on the port that is being used. 11. read the hcrhportstatus[1] and hcrhportstatus[2] registers. depending on which port the usb device is connected to, one of the registers should contain the hexadecimal value 0x00010103. sof packets should be visible on dp and dm now. the hcfmnumber register contains the current frame number, which is updated every milliseconds. remark: the generation of sof is completely performed by the isp1362 hardware. in this state of operation, if a ptd is written to the buffer memory, it would be processed and sent.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 41 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.3 usb ports the isp1362 has two usb ports: port 1 and port 2. port 1 can be con gured as a downstream port (host), an upstream port (device) or a dual-role port (otg). port 2 is a xed downstream port. the function of port 1 depends on two input pins of the isp1362, namely id and o tgmode. in the otg mode, port 2 operates as an internal host. it is not advisable to expose the host port 2 to external devices because it will not respond to the srp and hnp protocols. besides, the current capability of v bus may be different from the otg port s. the usb compliance checklist states that one and only one usb mini-ab receptacle is allowed on an otg device. 12.4 philips transfer descriptor (ptd) the ptd provides a communication channel between the hcd and the isp1362 usb hc. a ptd consists of a ptd header and a payload data. the size of the ptd header is 8 bytes, and it contains information required for data transfer, such as data packet size, transfer status and transfer token types. payload data to be transferred within a particular frame must have a ptd as the header (see figure 22 ). the isp1362 has three types of ptds: control and bulk transfer (aperiodic transfer) ptd, interrupt transfer ptd and isochronous (iso) transfer ptd. in the control and bulk transfer ptd and the interrupt transfer ptd, the buffer area is separated into equal sized blocks that are determined by hcatlblksize and hcintlblksize. for example, if the block size is de ned as 32 bytes, the rst ptd structure in the memory buffer will have an offset of 0 bytes and the second ptd structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the ptd header size (8 bytes)]. because of the xed block size of the isp1362 hc, however, even a ptd with 4 bytes of payload will occupy all the 40 bytes in a block. in the isochronous ptd, the hc uses a more exible method to calculate the ptd offset because each ptd can have a different payload size. the actual amount of space for the payload, however, must be a multiple of dword. therefore, a 10-byte payload must have a reserved data size of 12 bytes. take for example there are four ptds in the istl0 buffer area with payload sizes of 200 bytes, 10 bytes, 1023 bytes and 30 bytes. then, the offset of each of these ptds will be as follows: ptd1 (200 bytes) offset = 0 ptd2 (10 bytes) offset = (200 + 8) = 208 ptd3 (1023 bytes) offset = (200 + 8) + (12 + 8) = 228 ptd4 (30 bytes) offset = (200 + 8) + (12 + 8) + (1024 + 8) = 1260. table 8: port 1 function o tgmode id function of port 1 lxotg h l host h h peripheral
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 42 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. ptd data stored in the hc buffer memory will not be processed unless the respective control bits (atl_active, intl_active, istl0_bufferfull or istl1_bufferfull) in hcbufferstatus are set. ptd data in the atl or interrupt buffer memory can be disabled by setting the respective skip bit in hcatlskipmap and hcintlskipmap. to skip a particular ptd in the atl or interrupt buffer, the hcd may set the corresponding bit of the skipmap register. for example, setting the hcatlskipmap register to 0x0011 will cause the hc to skip the rst and the fth ptds in the atl buffer memory. certain elds in the ptd header are used by the hc to inform the hcd about the status of the transfer. these elds are indicated by the status update by hc column. these elds are updated after every transaction to re ect the current status of the ptd. [1] all reserved bits should be set to logic 0. fig 22. ptd data stored in the buffer memory. 004aaa121 ptd header buffer memory payload data ptd data #1 ptd header payload data payload data ptd header ptd data #2 ptd data #n top bottom table 9: generic ptd structure: bit allocation bit 7 6 5 4 3 2 1 0 byte 0 actualbytes[7:0] byte 1 completioncode[3:0] active toggle actualbytes[9:8] byte 2 maxpktsize[7:0] byte 3 endpointnumber[3:0] b3[3] speed maxpktsize[9:8] byte 4 totalbytes[7:0] byte 5 b5[7] b5[6] reserved dirtoken[1:0] totalbytes[9:8] byte 6 reserved functionaddress[6:0] byte 7 b7[7:0]
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 43 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] all reserved bits should be set to logic 0. table 10: special elds for atl, interrupt and iso [1] bit atl interrupt istl (iso) b3[3] reserved reserved last b5[6] ping-pong reserved reserved b5[7] paired reserved reserved b7[7:0] reserved pollingrate[7:5]; startingframe[4:0] startingframe table 11: generic ptd structure: bit description name status update by hc description actualbytes[9:0] yes this eld contains the number of bytes that were transferred for this ptd. completioncode[3:0] yes 0000 noerror general transfer descriptor (td) or isochronous data packet processing completed with no detected errors. 0001 crc the last data packet from the endpoint contained a cyclic redundancy check (crc) error. 0010 bitstuf ng the last data packet from the endpoint contained a bit stuf ng violation. 0011 datatogglemismatch the last packet from the endpoint had data toggle packet id (pid) that did not match the expected value. 0100 stall td was moved to the done queue because the endpoint returned a stall pid. 0101 devicenot responding the device did not respond to the token (in) or did not provide a handshake (out). 0110 pidcheckfailure the check bits on pid from the endpoint failed on data pid (in) or handshake (out). 0111 unexpectedpid the received pid was not valid when encountered, or the pid value is not de ned. 1000 dataoverrun the amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the maximumpacketsize eld of ed) or the remaining buffer size. 1001 dataunderrun the endpoint returned is less than maximumpacketsize and that amount was not suf cient to ll the speci ed buffer. 1010 - reserved 1011 - reserved 1100 bufferoverrun during an in, the hc received data from the endpoint faster than it could be written to the system memory. 1101 bufferunderrun during an out, the hc could not retrieve data from the system memory fast enough to keep up with the usb data rate.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 44 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.5 features of the control and bulk transfer (aperiodic transfer) a paired ptd is a special feature that provides high performance single endpoint bulk transfer and handles set-up enumeration sequence within 1 ms. a paired ptd consists of two ptds serving the same endpoint of a device that are set active and active yes set to logic 1 by rmware to enable the execution of transactions by the hc. when the transaction associated with this descriptor is completed, the hc sets this bit to logic 0 indicating that a transaction for this element should not be executed when it is next encountered in the schedule. toggle yes this bit is used to generate or compare the data pid value (data0 or data1) for in and out transactions. it is updated after each successful transmission or reception of a data packet. maxpktsize[9:0] no this indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. endpointnumber[3:0] no this is the usb address of the endpoint within the function. b3[3] last (ptd) no this indicates that it is the last ptd of a list. logic 1 means that this ptd is the last ptd. the last ptd is used only for iso. this bit is not used in interrupt and atl transfers. the last ptd is indicated by the hcintllastptd and hcatllastptd registers. speed (low) no this bit indicates the speed of the endpoint. 0 full-speed 1 low-speed totalbytes[9:0] no this speci es the total number of bytes to be transferred with this data structure. this can be greater than maximumpacketsize. b5[6] ping-pong no 0 this is the ping buffer of the paired buffer. paired must be logic 1. 1 this is the pong buffer of the paired buffer. paired must be logic 1. b5[7] paired no if this bit is set to logic 1, two ptds of the same endpoint and address can be made active at the same time. this bit is used with the ping-pong bit. the rst paired ptd always starts with ping = 0. the pong ptd payload can be sent out only if the ping ptd payload is sent out. you can also monitor ram_buffer _status to see which ptd is currently active on the usb line. dirtoken[1:0] no 00 set-up 01 out 10 in 11 reserved functionaddress[6:0] no this eld contains the usb address of the function containing the endpoint that this ptd refers to. b7[7:5] pollingrate b7[4:0] startingframe (interrupt only) no these two elds together select a start frame number (5 bits) and polls the interrupt device at a rate speci ed by pollingrate (3 bits); see section 12.6 . b7[7:0] startingframe (iso only) no the hc compares this byte with the current frame number (can be accessed from the hcframenumber register). the ptd will be processed and sent out only if the starting frame number equals to the current frame number. table 11: generic ptd structure: bit description continued name status update by hc description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 45 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. placed in the atl ram at the same time. a paired ptd is designed specially for high performance of a single endpoint. they are identi ed by hardware by using the paired bit in the ptd. possible to send up to a maximum of 18 usb bulk packets in 1 ms frame (1.152 mbyte/s) by using the paired ptd feature. provides the status of every transfer endpoints (ptd) by monitoring the hcatldonemap of the isp1362. this register provides information on which ptd transfers are complete. sets the irq after the user-speci ed number of transfers is done. skips any ptd that is wasting bandwidth by using hcatlskipmap. 12.5.1 sending a usb device request (get descriptor) this section provides an example on how a usb transfer descriptor get descriptor (commonly used in device enumeration) is used to illustrate the isp1362 ptd application. to perform this example, make sure the isp1362 is in the operational state, and then connect a usb device (for example, a usb mouse) to a port. remark: for details on the usb device request, refer to chapter 9 of universal serial bus speci cation rev. 2.0 . step 1: set the hcatlblksize, hcatlskip and hcatllast registers to 0x0008, 0xfffe and 0x0001, respectively. step 2: a ptd is then constructed based on the information given in the following sample code. this sample code places information into the correct bit location within the 8 bytes of the ptd structure. actualbytes (10 bits) = 0x00 completioncode (4 bits) = 0x0f active (1 bit) = 1 toggle (1 bit) = 0 maxpacketsize (10 bits) = 8 endpointnumber (4 bits) = 0 speed (1 bit) = 0 (full-speed; use 1 for low-speed) dirtoken (2 bits) = 0 (setup token) totalbytes (10 bits) = 8 completedptd 0xf800, 0x0008, 0x0008, 0x0000 step 3: this array is then appended with an 8-byte payload that speci es the type of request the hc wants to send. for example, for get descriptor, the payload is 0x0680, 0x0100, 0x0000, 0x0012. step 4: the 16 bytes of data is now a complete ptd with an accompanying payload. this array is then copied into the atl buffer area. ta b l e 1 2 shows the atl buffer area. step 5: after copying data into the atl buffer, the hc must be noti ed that the atl buffer is now full and ready to be processed. the atl_active bit of the hcbufferstatus register must be set to logic 1 to inform the hc that the data in the table 12: atl buffer area offset 0 1 2 3 4 5 6 7 data 0xf800 0x0008 0x0008 0x0000 0x0680 0x0100 0x0000 0x0012
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 46 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. atl buffer is now ready for processing. once the atl_active bit of the hcbufferstatus register is set, the usb packet is sent out. the active bit in the ptd is cleared once the ptd is sent. depending on the outcome of the usb transfer, the 4-bit completion code is updated. 12.6 features of the interrupt transfer an interrupt transaction is sent out periodically, according to the interrupt polling rate as de ned in the ptd. an interrupt transaction causes an interrupt to the cpu only if the transaction is acked or has error conditions, such as stall or no respond. an ack condition occurs if data is received on the in token or data is sent out on the out token. an interrupt is activated only once every ms as long as there is ack for different interrupt transactions in the interrupt transfer buffer. each interrupt transfer (ptd) placed in the intl buffer can automatically hold or send data for more than 1 ms. this can be done using the parameters in the ptd. 12.7 features of the isochronous (iso) transfer supports multi-buffering by using the istl0 or istl1 toggling mechanism. the cpu can decide (in ms) how fast it can serve the isp1362. this gives the cpu the exibility to decide how much time it takes to read and ll in the iso data. the istl buffer can be updated on-the- y by using the direct addressing memory architecture. 12.8 overcurrent protection circuit the isp1362 has a built-in overcurrent protection circuitry. you can enable or disable this feature by setting or resetting analogocenable (bit 10) of the hchardwarecon guration register. if this feature is disabled, it is assumed that there is an external overcurrent protection circuitry. table 13: interrupt polling n bits [7:5] startingframe n[4:0] interrupt polling interval (2 n ) in ms 0 frame 0 to 31 1 1 frame 0 to 31 2 2 frame 0 to 31 4 3 frame 0 to 31 8 4 frame 0 to 31 16 5 frame 0 to 31 32 6 frame 0 to 31 64 7 frame 0 to 31 128
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 47 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.8.1 using internal oc detection circuit an application using the internal oc detection circuit and internal 15 k ? pull-down resistors is shown in figure 23 , where dmn denotes either otg_dm1 or h_dm2, while dpn denotes either otg_dp1 or h_dp2. in this example, the hc driver must set both analogocenable and connectpulldown_ds1 (bit 10 and bit 12 of the hchardwarecon guration register, respectively) to logic 1. when h_ocn detects an overcurrent status on a downstream port, h_pswn will output high to turn off the 5 v power supply to the downstream port v bus . when there is no such detection, h_pswn will output low to turn on the 5 v power supply to the downstream port v bus . in general applications, you can use a p-channel mosfet as the power switch for v bus . connect the 5 v power supply to the source pole of the p-channel mosfet, v bus to the drain pole, and h_pswn to the gate pole. this voltage drop ( ? v) across the drain and source poles can be called the overcurrent trip voltage. for the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold of 75 mv. therefore, when the overcurrent trip voltage ( ? v) exceeds the voltage threshold, h_pswn will output a high level to turn off the p-channel mosfet. if the p-channel mosfet has r dson of 150 m ? , the overcurrent threshold will be 500 ma. the selection of a p-channel mosfet with a different r dson will result in a different overcurrent threshold. 12.8.2 using external oc detection circuit when v cc (pin 56) is connected to the 3.3 v power supply instead of the 5 v power supply, the internal oc detection circuit cannot be used. an external oc detection circuit must be used instead. nevertheless, regardless of v cc connection, an external oc detection circuit can be used from time to time. to use an external oc detection (1) 100 f for the host port or 4.7 f for the otg port. fig 23. using internal oc detection circuit. 004aaa148 h_ocn h_pswn v bus dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd psu_5v v dd_5v c17 0.1 f dgnd dgnd fb2 p_channel mosfet c18 0.1 f r31 10 k ? source drain gate
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 48 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. circuit, set analogocenable, bit 10 of register hchardwarecon guration, to logic 0. by default after reset this bit is set to logic 0. therefore, the hc driver does not need to clear this bit. figure 24 shows how to use an external oc detection circuit. 12.8.3 oc detection circuit using internal charge pump in the otg mode when port 1 is operating in the otg mode, you may choose to use the internal charge pump to provide 5 v v bus , or supply v bus from an external source. in this mode, the overcurrent condition is detected by a drop in v bus that will be sensed by the built-in comparator. the overcurrent condition causes a change in the a_vbus_vld bit of the otgstatus register. the software has to clear the drv_vbus bit in the otgcontrol register when it detects the a_vbus_vld bit turning to logic 0. (1) 100 f for the host port or 4.7 f for the otg port. fig 24. using external oc detection circuit. 004aaa149 h_ocn v bus oc en v in v out oc detection psu_5v dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd c17 0.1 f dgnd dgnd fb2 h_pswn
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 49 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.8.4 oc detection circuit using external 5 v power source in the otg mode in the otg mode using external 5 v power source for v bus , the circuit and the operation are the same as that for the non-otg mode (see section 12.8.1 and section 12.8.2 ). 12.9 isp1362 hc power management in the isp1362, the hc and the dc are suspended and waken up individually. the h_suspend/ h_w akeup and d_suspend/ d_w akeup pins must be pulled-up by a large resistor (100 k ? ). in the suspend state, these pins are high. to wake up the hc, these pins must be pulled low. the isp1362 can be partially suspended (only the hc or only the dc). in the partially suspended state, clock circuit and pll continue to work. to save power, both the hc and the dc must be set to the suspend mode. the hc can be suspended by writing 0x06c0 to the hccontrol register. the hc can be set awake by one of the following ways: low pulse on the h_suspend/ h_w akeup pin, minimum length of pulse is 25 ns. low pulse on the chip select ( cs) pin, minimum length of pulse is 25 ns. resume signal by usb devices connected to the downstream port. on waking up from the suspend state, the clock to the hc will sustain for 5 ms. within this 5 ms, the hc driver must set the hc to the operational mode by writing 0x0680 to the hccontrol register. if the hccontrol register remains in the suspend state (0x06c0) after waking up the hc, the hc will return to the suspend state after 5 ms. (1) 100 f for the host port or 4.7 f for the otg port. fig 25. using internal charge pump. 004aaa150 v bus dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd c17 0.1 f dgnd dgnd fb2 v bus n.c. h_ocn h_pswn
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 50 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. usb device controller (dc) the design of the dc in the isp1362 is compatible with the philips isp1181b usb full-speed interface device ic. the functionality of the dc in the isp1362 is similar to the isp1181b in the 16-bit bus mode. in addition, the command and register sets are also the same. in general, the dc in the isp1362 provides 16 endpoints for the usb device implementation. each endpoint can be allocated ram space in the on-chip ping pong buffer ram. remark: the ping pong buffer ram for the dc is independent of the buffer ram for the host controller (hc). when the buffer ram is full, the dc transfers the data in the buffer ram to the usb bus. when the buffer ram is empty, an interrupt is generated to notify the microprocessor to feed in data. the transfer of data between a microprocessor and the dc can be done in either the programmed i/o (pio) mode or in the direct memory access (dma) mode. 13.1 dc data transfer operation the following sessions explains how the dc in the isp1362 handles an in data transfer and an out data transfer. an in data transfer means transfer from the isp1362 to an external usb host (through the upstream port), and an out transfer means transfer from an external usb host to the isp1362. in the device mode, the isp1362 acts as a usb device. 13.1.1 in data transfer the arrival of the in token is detected by the serial interface engine (sie) by decoding the packet identi er (pid). the sie also checks the device number and the endpoint number to verify whether they are okay. if the endpoint is enabled, the sie checks the contents of the dcendpointstatus register (esr). if the endpoint is full, the contents of the buffer memory are sent during the data phase else an nak handshake is sent. after the data phase, the sie expects a handshake (ack) from the host (except for iso endpoints). on receiving the handshake (ack), the sie updates the contents of the dcendpointstatus and dcinterrupt registers, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is sent because there is no handshake phase. on receiving an interrupt, the microprocessor reads the dcinterrupt register. it will know which endpoint has generated the interrupt and reads the contents of the corresponding esr. if the buffer is empty, it lls up the buffer so that data can be sent by the sie at the next in token phase. 13.1.2 out data transfer the arrival of the out token is detected by the sie by decoding the pid. the sie checks the device and endpoint numbers to verify whether they are okay.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 51 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. if the endpoint is enabled, the sie checks the contents of the esr. if the endpoint is empty, the data from usb is stored in the buffer memory during the data phase else a nak handshake is sent. after the data phase, the sie sends a handshake (ack) to the host (except for iso endpoints). the sie updates the contents of the dcendpointstatus register and the dcinterrupt register, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is received because there is no handshake phase. on receiving an interrupt, the microprocessor reads the dcinterrupt register. it will know which endpoint has generated the interrupt and reads the content of the corresponding esr. if the buffer is full, it empties the buffer so that data can be received by the sie at the next out token phase. 13.2 device dma transfer 13.2.1 dma for in endpoint (internal dc to the external usb host) when the internal dma handler is enabled and at least one buffer (ping or pong) is free, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus. as soon as it has access, it asserts the d a ck2 line and starts writing data. the burst length is programmable. when the number of bytes equal to the burst length has been written, the dreq2 line is deasserted. as a result, the dma controller deasserts the d a ck2 line and releases the bus. at that moment, the whole cycle restarts for the next burst. when the buffer is full, the dreq2 line is deasserted and the buffer is validated (which means that it is sent to the host at the next in token). when the dma transfer is terminated, the buffer is also validated (even if it is not full). a dma transfer is terminated when any of the following conditions are met: the dma count is complete dmaen = 0. remark: if the onedma bit in the hchardwarecon guration register is set to logic 1, the dc dma controller handshake signals dreq2 and d a ck2 are routed to dreq1 and d a ck1. 13.2.2 dma for out endpoint (external usb host to internal dc) when the internal dma handler is enabled and at least one buffer is full, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the d a ck2 line and starts reading data. the burst length is programmable. when the number of bytes equal to the burst length has been read, the dreq2 line is deasserted. as a result, the dma controller deasserts the d a ck2 line and releases the bus. at that moment, the whole cycle restarts for the next burst. when all the data is read, the dreq2 line is deasserted and the buffer is cleared (this means that it can be overwritten when a new packet arrives). a dma transfer is terminated when any of the following conditions are met: the dma count is complete dmaen = 0.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 52 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: if the onedma bit in the hchardwarecon guration register is set to logic 1, the dc dma controller handshake signals dreq2 and d a ck2 are routed to dreq1 and d a ck1. when the dma transfer is terminated, the buffer is also cleared (even if data is not completely read) and the dma handler is automatically disabled. for the next dma transfer, the dma controller as well as the dma handler must be re-enabled. 13.3 endpoint description 13.3.1 endpoints with programmable buffer memory size each usb device is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ow between the usb host and the usb device. at design time, each endpoint is assigned a unique number (endpoint identi er, see ta b l e 1 4 ). the combination of the device address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. the dc has 16 endpoints: endpoint 0 (control in and out) and 14 con gurable endpoints, which can be individually de ned as interrupt, bulk or isochronous in or out. each enabled endpoint has an associated buffer memory, which can be accessed either by using the programmed i/o interface mode or by using the dma mode. 13.3.2 endpoint access ta b l e 1 4 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support the dma mode access. dc buffer memory dma access is selected and enabled using bits epidx[3:0] and dmaen of the dcdmacon guration register. a detailed description of the dc dma operation is given in section 13.4 . [1] the total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes. [2] in: input for the usb host (dc transmits); out: output from the usb host (dc receives). [3] the data ow direction is determined by the epdir bit of the dcendpointcon guration register. 13.3.3 endpoint buffer memory size the size of the buffer memory determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared buffer memory storage, disabled endpoints have zero bytes. ta b l e 1 5 lists the programmable buffer memory sizes. the following bits of the dcendpointcon guration register (ecr) affect the buffer memory allocation: endpoint enable bit (fifoen) table 14: endpoint access and programmability endpoint identi er buffer memory size (bytes) [1] double buffering pio mode access dma mode access endpoint type 0 64 ( xed) no yes no control out [2][3] 0 64 ( xed) no yes no control in [2][3] 1 to 14 programmable supported supported supported programmable
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 53 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. size bits of an enabled endpoint (ffosz[3:0]) isochronous bit of an enabled endpoint (ffoiso). remark: a register change that affects the allocation of the shared buffer memory storage among endpoints must not be made while valid data is present in any buffer memory of the enabled endpoints. such changes renders all buffer memory contents unde ned. each programmable buffer memory can be independently con gured by using its ecr, but the total physical size of all enabled endpoints (in plus out) must not exceed 2462 bytes. ta b l e 1 6 shows an example of a con guration tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. table 15: programmable buffer memory size ffosz[3:0] non-isochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 16: memory con guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64-byte xed) 64 64 control out (64-byte xed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt out 16 16 16-byte interrupt in 128 64 double-buffered 64-byte bulk out 128 64 double-buffered 64-byte bulk in
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 54 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.4 endpoint initialization in response to the standard usb request set interface, the rmware must program all the 16 ecrs of the dc in sequence (see ta b l e 1 4 ), whether endpoints are enabled or not. the hardware then automatically allocates buffer memory storage space. if all endpoints have been successfully con gured, the rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con guration, the rmware must stall the control in endpoint. when reset by hardware or by the usb bus occurs, the dc disables all endpoints and clears all ecrs, except the control endpoint which is xed and always enabled. an endpoint initialization can be done at any time. it is, however, valid only after enumeration. 13.3.5 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the dcinterrupt register (ir) are set by the sie. the rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit is cleared by reading the dcendpointstatus register (esr). the esr also contains information on the status of the endpoint buffer. for an out (= receive) endpoint, the packet length and packet data can be read from the dc by using the read buffer command. when the whole packet has been read, the rmware sends a clear buffer command to enable the reception of new packets. for an in (= transmit) endpoint, the packet length and data to be sent can be written to the dc by using the write buffer command. when the whole packet has been written to the buffer, the rmware sends a validate buffer command to enable data transmission to the host. 13.3.6 special actions on control endpoints control endpoints require special rmware actions. the arrival of a set-up packet ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor needs to re-enable these commands by sending an acknowledge set-up command to both the control endpoints. this ensures that the last set-up packet stays in the buffer and that no packets can be sent back to the host until the microprocessor has explicitly acknowledged that it has received the set-up packet. 13.4 dc direct memory access (dma) transfer dma is a method to transfer data from one location to another in a computer system, without intervention of the cpu. many different implementations of dma exist. the dc supports the 8237 compatible mode. 8237 compatible mode : based on the dma subsystem of the ibm personal computers (pc, at and all its successors and clones); this architecture uses the intel 8237 dma controller and has separate address spaces for memory and i/o.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 55 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following features are supported: single-cycle or burst transfers (up to 16 bytes per cycle) programmable transfer direction (read or write) multiple end-of-transfer (eot) sources: internal conditions, short or empty packet programmable signal levels on pins dreq2 and d a ck2. 13.4.1 selecting an endpoint for the dma transfer the target endpoint for dma access is selected using bits epdix[3:0] of the dcdmacon guration register, as shown in ta b l e 1 7 . the transfer direction (read or write) is automatically set by the epdir bit in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). asserting input d a ck2 automatically selects the endpoint speci ed in the dcdmacon guration register, regardless of the current endpoint used for the i/o mode access. 13.4.2 8237 compatible mode the 8237 compatible dma mode is selected by clearing the dakoly bit of the dchardwarecon guration register (see table 114 ). the pin functions for this mode are shown in ta b l e 1 8 . table 17: endpoint selection for dma transfer endpoint identi er epidx[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write 10 1011 out: read in: write 11 1100 out: read in: write 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write table 18: 8237 compatible mode: pin functions symbol description i/o function dreq2 dma request of dc o dc requests a dma transfer d a ck2 dma acknowledge of dc i dma controller con rms the transfer eot end of transfer i dma controller terminates the transfer rd read strobe i instructs the dc to put data on the bus wr write strobe i instructs the dc to get data from the bus
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 56 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the dma subsystem of an ibm-compatible pc is based on the intel 8237 dma controller. it operates as a y-by dma controller. data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of the dc in 8237 compatible dma mode is given in figure 26 . the 8237 has two control signals for each dma channel: dreq (dma request) and d a ck (dma acknowledge). general control signals are hrq (hold request) and hlda (hold acknowledge). the bus operation is controlled by memr (memory read), memw (memory write), ior (i/o read) and io w (i/o write). the following example shows the steps that occur in a typical dma transfer: 1. the dc receives a data packet in one of its endpoint buffer memory. the packet must be transferred to memory address 1234h. 2. the dc asserts the dreq2 signal requesting the 8237 for a dma transfer. 3. the 8237 asks the cpu to release the bus by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 now sets its address lines to 1234h and activates the memw and ior control signals. 6. the 8237 asserts d a ck to inform the dc that it will start a dma transfer. 7. the dc now places the word to be transferred on the data bus lines because its rd signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then deasserts memw and ior. this latches and stores the word at the desired memory location. it also informs the dc that the data on the bus lines has been transferred. 9. the dc deasserts the dreq2 signal to indicate to the 8237 that dma is no longer needed. in the single cycle mode, this is done after each byte or word; in the burst mode , following the last transferred byte or word of the dma cycle. 10. the 8237 deasserts the d a ck output indicating that the dc must stop placing data on the bus. fig 26. dc in 8327 compatible dma mode. d0 to d15 cpu 004aaa047 ram isp1362 dma controller 8237 dreq2 dack2 dreq hrq hlda hrq hlda dack ior iow memr memw rd wr
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 57 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. the 8237 places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and deasserts the hrq signal, informing the cpu that it has released the bus. 12. the cpu acknowledges control of the bus by deasserting hlda. after activating the bus control lines ( memr, memw, ior and io w) and the address lines, the cpu resumes the execution of instructions. for a typical bulk transfer, the preceding process is repeated 32 times, once for each word. after each word, the dcaddress register in the dma controller is incremented by two and the byte counter is decremented by two. when using the 16-bit dma, the number of transfers is 32 and address incrementing and byte counter decrementing is done by two for each word. 13.4.3 end-of-transfer conditions bulk endpoints: a dma transfer to or from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon guration register, see table 118 and table 119 ): the dma transfer completes as programmed in the dcdmacounter register (cntren = 1) a short packet is received on an enabled out endpoint (shortp = 1) dma operation is disabled by clearing the dmaen bit. dcdmacounter register an eot from the dcdmacounter register is enabled by setting bit cntren of the dcdmacon guration register. the dc has a 16-bit dcdmacounter register, which speci es the number of bytes to be transferred. when dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dcdmacounter register. when the internal counter completes the transfer as programmed in the dma counter, an eot condition is generated and the dma operation stops. short packet normally, the transfer byte count must be set using a control endpoint before any dma transfer takes place. when a short packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short packet in the data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short packet at an out token will stop the dma operation after transferring the data bytes of this packet. [1] the dma transfer stops. no interrupt, however, is generated. table 19: summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint dcdmacounter register transfer completes as programmed in the dcdmacounter register transfer completes as programmed in the dcdmacounter register short packet short packet is received and transferred counter reaches zero in the middle of the buffer dmaen bit of the dcdmacon guration register dmaen = 0 [1] dmaen = 0 [1]
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 58 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. isochronous endpoints: a dma transfer to or from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon guration register, see table 118 and table 119 ): the dma transfer completes as programmed in the dcdmacounter register (cntren = 1) an end-of-packet (eop) signal is detected dma operation is disabled by clearing bit dmaen. 13.5 isp1362 dc suspend and resume 13.5.1 suspend conditions the dc in the isp1362 detects a usb suspend condition in either of the following cases: constant idle state is present on the usb bus for 3 ms. v bus is lost. bus-powered devices that are suspended must not consume more than 500 a of current. this is achieved by shutting down the power to system components or supplying them with a reduced voltage. the steps leading the dc to the suspend state are as follows: 1. in the event of no sof for 3 ms, the dc in the isp1362 sets bit suspnd of the dcinterrupt register. this will generate an interrupt if bit iesusp of the dcinterruptenable register is set. 2. when the rmware detects a suspend condition (through the iesusp), it must prepare all system components for the suspend state: a. all the signals connected to the dc in the isp1362 must enter appropriate states to meet the power consumption requirements of the suspend state. b. all the input pins of the dc in the isp1362 must have a cmos logic 0 or logic 1 level. 3. in the interrupt service routine, the rmware must check the current status of the usb bus. when bit bustatus of the dcinterrupt register is logic 0, the usb bus has left the suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit clkrun of the dchardwarecon guration register. 5. when the rmware has set and cleared the gosusp bit of the dcmode register, the dc in the isp1362 enters the suspend state. it sets the d_suspend/ d_w akeup pin to high and switches off the internal clocks after 2ms. table 20: recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint dcdmacounter register zero do not use preferred
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 59 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the dc in the isp1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traf c, cs active or low pulse on the d_suspend/ d_w akeup pin. figure 27 shows a typical timing diagram for the dc suspend and resume operations. in figure 27 : a indicates the point at which the usb bus goes to the idle state. b after detecting the suspend interrupt, set and clear the gosusp bit in the mode register. c indicates resume condition, which can be a resume signal from the host, a low pulse on the d_suspend/ d_w akeup pin, or a low pulse on the cs pin. d indicates remote wake-up. the isp1362 will drive a k-state on the usb bus for 10 ms after the d_suspend/ d_w akeup pin goes low or the cs pin goes low. 13.5.2 resume conditions wake-up from the suspend state is initiated either by the usb host or by the application: usb host: drives a k-state on the usb bus (global resume) application: remote wake-up using a low pulse on pin d_suspend/ d_w akeup or a low pulse on pin cs (if enabled using bit wkupcs of the dchardwarecon guration register). the steps of a wake-up sequence are as follows: fig 27. suspend and resume timing. 004aaa483 int2 > 5 ms suspend interrupt usb bus gosusp (bit) cs idle state 10 ms k-state > 3 ms 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms resume interrupt a d b c d_suspend/d_wakeup
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 60 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, the clock signals are routed to all internal circuits of the dc in the isp1362. 2. the d_suspend/ d_w akeup pin goes low, and the resume bit of the dcinterrupt register is set. this will generate an interrupt if bit ieresume of the dcinterruptenable register is set. 3. 5 ms after starting the wake-up sequence, the dc in the isp1362 resumes its normal functionality (this could be set to 100 s by setting pin test0 to high). 4. in case of a remote wake-up, the dc in the isp1362 drives a k-state on the usb bus for 10 ms. 5. the application restores itself and other system components to normal operating mode. 6. after wake-up, the internal registers of the dc in the isp1362 are read and write-protected to prevent corruption by inadvertent writing during power-up of external components. the rmware must send an unlock device command to the dc in the isp1362 to restore its full functionality. 14. otg registers 14.1 otgcontrol register (r/w: 62h/e2h) code (hex): 62 read code (hex): e2 write table 21: otg control registers summary command (hex) register width references functionality read write 62 e2 otgcontrol 16 section 14.1 on page 60 otg operation registers 67 n/a otgstatus 16 section 14.2 on page 62 68 e8 otginterrupt 16 section 14.3 on page 63 69 e9 otginterruptenable 16 section 14.4 on page 66 6a ea otgtimer 32 section 14.5 on page 67 6c ec otgalttimer 32 section 14.6 on page 68 table 22: otgcontrol register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_se0_ en a_srp_ det_en a_sel_ srp sel_hc_ dc reset ---- 0001 access ----r/wr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol loc_ pulldn_ dm loc_ pulldn_ dp a_rdis_ lcon_en loc_ conn sel_cp_ ext dischrg_ vbus chrg_ vbus drv_ vbus reset 11000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 61 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 23: otgcontrol register: bit description bit symbol description 15 to 12 - reserved 11 otg_se0_ en this bit is used by the hc to send se0 on remote connect. 0 no se0 sent on remote connect detection 1 se0 (bus reset) sent on remote connect detection remark: this bit is normally set when the b-device goes into the b_wait_acon state (recommended sequence: loc_conn = 0 -> delay -> 50 s -> otg_se0_en = 1 -> sel_hc_dc = 0) and is cleared when it comes out of the b_wait_acon state. 10 a_srp_ det_en this bit is for the a-device only. if set, the a_srp_det bit in the otginterrupt register will be set on detecting an srp event. 0 disable 1 enable 9 a_sel_ srp this bit is for the a-device to select a method for detecting the srp event (v bus pulsing or data line pulsing). 0 a-device responds to v bus pulsing 1 a-device responds to data line pulsing 8 sel_hc_ dc this bit is used to select either the dc or the hc that interfaces with the transceiver. 0 hc sie is connected to the otg transceiver 1 dc sie is connected to the otg transceiver 7 loc_ pulldn_ dm 0 disconnects the on-chip pull-down resistor on dm of the otg port 1 connects the on-chip pull-down resistor on dm of the otg port 6 loc_ pulldn_ dp 0 disconnects the on-chip pull-down resistor on dp of the otg port 1 connects the on-chip pull-down resistor on dp of the otg port 5 a_rdis_ lcon_en this bit is for the a-device only. if set, the chip will automatically enable its pull-up resistor on dp upon detecting a remote disconnect event. if cleared, the dp pull-up is controlled by the loc_conn bit. 0 disable 1 enable remark: this bit is normally set when the a-device goes into the a_suspend state and is cleared when it comes out of the a_suspend state. the loc_conn bit must be set before clearing this bit.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 62 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.2 otgstatus register (r: 67h) code (hex): 67 read only 4 loc_ conn 0 disconnect the on-chip pull-up resistor on dp of the otg port 1 connect the on-chip pull-up resistor on dp of the otg port 3 sel_cp_ ext this bit is for the a-device only. this bit is used to choose the power source to drive v bus . 0 use on-chip charge pump to drive v bus 1 use external power source (5 v) to drive v bus remark: when using the external power source, the h_psw1 pin serves as the power switch that is controlled by the drv_vbus bit of this register. 2 dischrg_ vbus this bit is for the b-device only. if set, it will enable a pull-down resistor on v bus , which will help to speed up discharging of v bus below session end threshold voltage. 0 disable 1 enable 1 chrg_ vbus this bit is for the b-device only. if set, it will charge v bus through a resistor. 0 disable charging v bus of the otg port 1 enable charging v bus of the otg port 0 drv_vbus this bit is used to enable the on-chip charge pump or external power source to drive v bus . for the b-device, it shall not enable this bit at any time. 0 disable driving v bus of the otg port 1 enable driving v bus of the otg port table 23: otgcontrol register: bit description continued bit symbol description table 24: otgstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved se0_2ms reserved reset ------0- access ------r- bit 7 6 5 4 3 2 1 0 symbol reserved rmt_ conn b_sess_ vld a_sess_ vld b_sess_ end a_vbus_ vld id_reg reset - - 000101 access - - rrrrrr
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 63 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.3 otginterrupt register (r/w: 68h/e8h) code (hex): 68 read code (hex): e8 write table 25: otgstatus register: bit description bit symbol description 15 to 10 - reserved 9 se0_2ms 0 bus is in se0 for less than 2 ms 1 bus is in se0 for more than 2 ms 8 to 6 - reserved 5 rmt_ conn 0 remote pull-up resistor disconnected 1 remote pull-up resistor connected remark: when the local pull-up resistor on the dp-line is disabled, a 50 s delay is applied before rmt_conn detection is enabled. 4 b_sess_vld for the b-device (id_reg = 1), this bit is a b-device session valid indicator (b_sess_vld). 0 v bus is lower than vb_sess_vld 1 v bus is higher than vb_sess_vld 3 a_sess_vld for the a-device (id_reg = 0), this bit is an a-device session valid indicator (a_sess_vld). 0 v bus is lower than va_sess_vld 1 v bus is higher than va_sess_vld 2 b_sess_end for the b-device (id_reg = 1), this bit is a b-device session end indicator (b_sess_end). 0 v bus is higher than vb_sess_end 1 v bus is lower than vb_sess_end 1 a_vbus_vld for the a-device (id_reg = 0), this bit is an a-device v bus valid indicator (a_vbus_vld). 0 v bus is lower than va_vbus_vld 1 v bus is higher than va_vbus_vld 0 id_reg this bit re ects the logic level of the id pin. 0 id pin is low (mini-a plug is inserted in the device s mini-ab receptacle) 1 id pin is high (no plug or mini-b plug is inserted in the device s mini-ab receptacle)
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 64 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 26: otginterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_tmr _timeout b_se0_ srp a_srp_ det reset -----000 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol otg_ resume otg_ suspnd rmt_ conn_c b_sess_ vld_c a_sess_ vld_c b_sess_ end_c a_vbus_ vld_c id_reg_c reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 27: otginterrupt register: bit description bit symbol description 15 to 11 - reserved 10 otg_tmr_ timeout this bit is set whenever the otg timer attains time-out. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 otg timer time-out 9 b_se0_ srp this bit is set whenever the device detects more than 2 ms of se0. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 bus has been in se0 for more than 2 ms 8 a_srp_ det this bit is used to detect the session request event (srp) from the remote device. the srp event can be either v bus pulsing or data line pulsing. bit 9 (a_sel_srp) of the otgcontrol register determines which srp is selected. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 srp is detected 7 otg_ resume this bit is used to detect a j to k state change when the device is in the suspend state. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 a resume signal (j k) is detected when the bus is in the suspend state
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 65 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6 otg_ suspnd this bit is set whenever the otg port goes into the suspend state (bus idle for > 3 ms). write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 suspend (bus idle for > 3 ms) 5 rmt_ conn_c this bit is set whenever the rmt_conn bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 rmt_conn bit has changed 4 b_sess_ vld_c this bit is set whenever the b_sess_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit b_sess_vld has changed 3 a_sess_ vld_c this bit is set whenever the a_sess_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit a_sess_vld has changed 2 b_sess_ end_c this bit is set whenever the b_sess_end bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit b_sess_end has changed 1 a_vbus_ vld_c this bit is set whenever the a_vbus_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit a_vbus_vld has changed 0 id_reg_c this bit is set whenever the id_reg bit of the otgstatus register changes. this is an indication that the mini-a plug is inserted or removed (that is, the id pin is shorted to ground or pulled high). write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 id_reg bit has changed table 27: otginterrupt register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 66 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.4 otginterruptenable register (r/w: 69h/e9h) code (hex): 69 read code (hex): e9 write table 28: otginterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_ tmr_ie b_se0_ srp_ie a_srp_ det_ie reset -----000 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol otg_ resume_ ie otg_ suspnd_ ie rmt_ conn_ie b_sess_ vld_ie a_sess_ vld_ie b_sess_ end_ie a_vbus_ vld_ie id_reg_ ie reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 29: otginterruptenable register: bit description bit symbol description 15 to 11 - reserved 10 otg_ tmr_ie logic 1 enables interrupt when the otg timer attains time-out. 9 b_se0_ srp_ie logic 1 enables interrupt upon detection of the b_se0_srp status change. 8 a_srp_ det_ie logic 1 enables interrupt upon detection of the srp event. 7 otg_ resume_ ie logic 1 enables interrupt upon detection of bus resume (j to k only) event. 6 otg_ suspnd_ ie logic 1 enables interrupt upon detection of the bus suspend status change. 5 rmt_ conn_ie logic 1 enables interrupt upon detection of the rmt_conn status change. 4 b_sess_ vld_ie logic 1 enables interrupt upon detection of b_sess_vld status change. 3 a_sess_ vld_ie logic 1 enables interrupt upon detection of a_sess_vld status change. 2 b_sess_ end_ie logic 1 enables interrupt upon detection of b_sess_end status change. 1 a_vbus_ vld_ie logic 1 enables interrupt upon detection of a_vbus_vld status change. 0 id_reg_ie logic 1 enables interrupt upon detection of the id_reg status change.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 67 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.5 otgtimer register (r/w: 6ah/eah) code (hex): 6a read code (hex): ea write table 30: otgtimer register: bit allocation bit 31 30 29 28 27 26 25 24 symbol start_ tmr reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol tmr_init_value[23:16] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol tmr_init_value[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol tmr_init_value[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 31: otgtimer register: bit description bit symbol description 31 start_ tmr this is the start or stop bit of the otg timer. writing logic 1 will cause the otg timer to load tmr_init_value into the counter and start to count. writing logic 0 will stop the timer. this bit is automatically cleared when the otg timer is timed out. 0 stop the timer 1 start the timer 30 to 24 - reserved 23 to 0 tmr_init_ value [23:0] these bits de ne the initial value used by the otg timer. the timer interval is 0.01 ms. maximum timer allowed is 167.772 s.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 68 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.6 otgalttimer register (r/w: 6ch/ech) code (hex): 6c read code (hex): ec write table 32: otgalttimer register: bit allocation bit 31 30 29 28 27 26 25 24 symbol start_ tmr reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol current_time[23:16] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol current_time[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol current_time[7:0] reset 00000000 access rrrrrrrr table 33: otgalttimer register: bit description bit symbol description 31 start_ tmr this is the start or stop bit of the otg timer 2. writing logic 1 will cause the otg timer 2 to start counting from 0. when the counter reaches ffffffh, this bit is auto-cleared (the counter is stopped). writing logic 0 will stop the counting. if any bit of the otginterrupt register is set and the corresponding bit of the otginterruptenable register is also set, this bit will be auto-cleared and the current value of the counter will be written to the current_time eld. 0 stop the timer 1 start the timer 30 to 24 - reserved 23 to 0 current_ time when read, these bits give the current value of the timer. the actual time is current_time 0.01 ms.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 69 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15. hc registers the hc contains a set of on-chip control registers. these registers can be read or written by the hc driver (hcd). the control and status register set, the frame counter register set and the root hub register set are grouped under the category of hc operational registers (32 bits). these operational registers are made compatible to open host controller interface (openhci) operational registers. this enables the openhci hcd to be ported easily to the isp1362. reserved bits may be de ned in future releases of this speci cation. to ensure interoperability, the hcd that does not use a reserved eld must not assume that the reserved eld contains logic 0. furthermore, the hcd must always preserve the values of the reserved eld. when a r/w register is modi ed, the hcd must rst read the register, modify the desired bits and then write the register with the reserved bits still containing the read value. alternatively, the hcd can maintain an in-memory copy of previously written values that can be modi ed and then written to the hc register. when there is a write to set or clear the register, bits written to reserved elds must be logic 0. as shown in ta b l e 3 4 , the offset locations (the commands for reading registers) of these operational registers (32-bit registers) are similar to those de ned in the ohci speci cation. the addresses, however, are equal to offset divided by 4. table 34: hc control registers summary command (hex) register width reference functionality read write 00 n/a hcrevision 32 section 15.1.1 on page 71 hc control and status registers 01 81 hccontrol 32 section 15.1.2 on page 71 02 82 hccommandstatus 32 section 15.1.3 on page 73 03 83 hcinterruptstatus 32 section 15.1.4 on page 74 04 84 hcinterruptenable 32 section 15.1.5 on page 75 05 85 hcinterruptdisable 32 section 15.1.6 on page 76 0d 8d hcfminterval 32 section 15.2.1 on page 78 hc frame counter registers 0e 8e hcfmremaining 32 section 15.2.2 on page 79 0f 8f hcfmnumber 32 section 15.2.3 on page 80 11 91 hclsthreshold 32 section 15.2.4 on page 81 12 92 hcrhdescriptora 32 section 15.3.1 on page 82 hc root hub registers 13 93 hcrhdescriptorb 32 section 15.3.2 on page 84 14 94 hcrhstatus 32 section 15.3.3 on page 85 15 95 hcrhportstatus[1] 32 section 15.3.4 on page 87 16 96 hcrhportstatus[2] 32 section 15.3.4 on page 87 20 a0 hchardwarecon guration 16 section 15.4.1 on page 92 hc dma and interrupt control registers 21 a1 hcdmacon guration 16 section 15.4.2 on page 94 22 a2 hctransfercounter 16 section 15.4.3 on page 95 24 a4 hc pinterrupt 16 section 15.4.4 on page 95 25 a5 hc pinterruptenable 16 section 15.4.5 on page 97
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 70 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 27 n/a hcchipid 16 section 15.5.1 on page 98 hc miscellaneous registers 28 a8 hcscratch 16 section 15.5.2 on page 98 n/a a9 hcsoftwarereset 16 section 15.5.3 on page 99 2c ac hcbufferstatus 16 section 15.6.1 on page 99 hc buffer ram control registers 32 b2 hcdirectaddresslength 32 section 15.6.2 on page 100 45 c5 hcdirectaddressdata 16 section 15.6.3 on page 101 30 b0 hcistlbuffersize 16 section 15.7.1 on page 101 iso transfer registers 40 c0 hcistl0bufferport 16 section 15.7.2 on page 101 42 c2 hcistl1bufferport 16 section 15.7.3 on page 102 47 c7 hcistltogglerate 16 section 15.7.4 on page 102 33 b3 hcintlbuffersize 16 section 15.8.1 on page 103 interrupt transfer registers 43 c3 hcintlbufferport 16 section 15.8.2 on page 103 53 d3 hcintlblksize 16 section 15.8.3 on page 104 17 n/a hcintlptddonemap 32 section 15.8.4 on page 104 18 98 hcintlptdskipmap 32 section 15.8.5 on page 105 19 99 hcintllastptd 32 section 15.8.6 on page 105 1a n/a hcintlcurrentactiveptd 16 section 15.8.7 on page 105 34 b4 hcatlbuffersize 16 section 15.9.1 on page 106 aperiodic transfer registers 44 c4 hcatlbufferport 16 section 15.9.2 on page 106 54 d4 hcatlblksize 16 section 15.9.3 on page 107 1b n/a hcatlptddonemap 32 section 15.9.4 on page 107 1c 9c hcatlptdskipmap 32 section 15.9.5 on page 108 1d 9d hcatllastptd 32 section 15.9.6 on page 108 1e n/a hcatlcurrentactiveptd 16 section 15.9.7 on page 108 51 d1 hcatlptddonethresholdcount 16 section 15.9.8 on page 109 52 d2 hcatlptddonethresholdtimeout 16 section 15.9.9 on page 109 table 34: hc control registers summary continued command (hex) register width reference functionality read write
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 71 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.1 hc control and status registers 15.1.1 hcrevision register (r: 00h) the bit allocation of the hcrevision register is given in ta b l e 3 5 . code (hex): 00 read only 15.1.2 hccontrol register (r/w: 01h/81h) the hccontrol register de nes the operating modes for the hc. the rwe bit is modi ed only by the hcd. ta b l e 3 7 shows the bit allocation of the register. code (hex): 01 read code (hex): 81 write table 35: hcrevision register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol rev[7:0] reset 00010001 access rrrrrrrr table 36: hcrevision register: bit description bit symbol description 31 to 8 ? reserved 7 to 0 rev[7:0] revision: this read-only eld contains the binary-coded decimal (bcd) representation of the version of the hci speci cation that is implemented by this hc. for example, a value of 11h corresponds to version 1.1. all hc implementations that are compliant with this speci cation need to have a value of 11h. table 37: hccontrol register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access --------
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 72 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved rwe rwc reserved reset -----00- access -----r/wr/w- bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] reserved reset 00------ access r/wr/w------ table 38: hccontrol register: bit description bit symbol description 31 to 11 - reserved 10 rwe remotewakeupenable: this bit is used by the hcd to enable or disable the remote wake-up feature on detecting upstream resume signaling. when this bit and the resumedetected (rd) bit in hcinterruptstatus are set, a remote wake-up is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remotewakeupconnected: this bit indicates whether the hc supports remote wake-up signaling. if remote wake-up is supported and used by the system, it is the responsibility of the system rmware to set this bit during post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wake-up signaling of the host system is host bus-speci c and is not described in this speci cation. 8 - reserved 7 to 6 hcfs[1:0] hostcontrollerfunctionalstate for usb 00 usbreset 01 usbresume 10 usboperational 11 usbsuspend a transition to usboperational from another state causes start-of-frame (sof) generation to begin 1 ms later. the hcd may determine whether the hc has begun sending sofs by reading the startofframe (sf) eld of hcinterruptstatus. this eld may be changed by the hc only when it is in the usbsuspend state. the hc may move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the hc enters usbreset after a software reset and a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 to 0 - reserved
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 73 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.1.3 hccommandstatus register (r/w: 02h/82h) the hccommandstatus register is a 4-byte register, and the bit allocation is given in ta b l e 3 9 . this register is used by the hc to receive commands issued by the hcd, and it also re ects the current status of the hc. to the hcd, it appears to be a write to set register. the hc must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the hc without concern for corrupting previously issued commands. the hcd has normal read access to all bits. the schedulingoverruncount (soc) eld indicates the number of frames with which the hc has detected the scheduling overrun error. this occurs when the periodic list does not complete before the end-of-frame (eof). when a scheduling overrun error is detected, the hc increments the counter and sets the schedulingoverrun (so) eld of the hcinterruptstatus register. code (hex): 02 read code (hex): 82 write table 39: hccommandstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved soc[1:0] reset ------00 access ------rr bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved hcr reset -------0 access -------r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 74 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.1.4 hcinterruptstatus register (r/w: 03h/83h) this register (bit allocation: ta b l e 4 1 ) provides the status of the events that cause hardware interrupts. when an event occurs, the hc sets the corresponding bit in this register. when a bit is set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register (see section 15.1.5 ) and the masterinterruptenable (mie) bit is set. the hcd may clear speci c bits in this register by writing logic 1 to the bit positions to be cleared. the hc, however, does not clear the bit. the hcd may not set any of these bits. code (hex): 03 read code (hex): 83 write table 40: hccommandstatus register: bit description bit symbol description 31 to 18 - reserved 17 to 16 soc[1:0] schedulingoverruncount: this eld is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it needs to be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by the hcd to monitor any persistent scheduling problems. 15 to 1 - reserved 0 hcr hostcontrollerreset: this bit is set by the hcd to initiate a software reset of the hc. regardless of the functional state of the hc, it moves to the usbsuspend state in which most of the operational registers are reset except those stated otherwise. this bit is cleared by the hc on completing the reset operation. the reset operation must be completed within 10 ms. this bit, when set, should not cause a reset to the root hub and no subsequent reset signaling should be asserted to its downstream ports. table 41: hcinterruptstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 75 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.1.5 hcinterruptenable register (r/w: 04h/84h) each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. when the following three conditions occur: a bit is set in the hcinterruptstatus register the corresponding bit in the hcinterruptenable register is set the masterinterruptenable (mie) bit is set. then, a hardware interrupt is requested on the host bus. writing logic 1 to a bit in the hcinterruptenable register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. ta b l e 4 3 contains the bit allocation of the register. code (hex): 04 read code (hex): 84 write table 42: hcinterruptstatus register: bit description bit symbol description 31 to 7 - reserved 6 rhsc roothubstatuschange: this bit is set when the content of hcrhstatus or the content of any of hcrhportstatus[numberofdownstreamport] has changed. 5 fno framenumberover ow: this bit is set when the msb of hcfmnumber (bit 15) changes from logic 0 to 1 or from logic 1 to 0. 4ue unrecoverableerror: this bit is set when the hc detects a system error not related to the usb. the hc should not proceed with any processing nor signaling before the system error has been corrected. the hcd clears this bit after the hc has been reset. philips host controller interface (phci): always set to logic 0. 3rd resumedetected: this bit is set when the hc detects that a device on the usb is asserting resume signaling. it is the transition from no resume signaling to resume signaling causing this bit to be set. this bit is not set when the hcd sets the usbresume state. 2sf startofframe: at the start of each frame, this bit is set by the hc and an sof is generated. 1 - reserved 0so schedulingoverrun: this bit is set when the usb schedules for current frame overruns. a scheduling overrun also causes the schedulingoverruncount (soc) of hccommandstatus to be incremented.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 76 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.1.6 hcinterruptdisable register (r/w: 05h/85h) each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas table 43: hcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w table 44: hcinterruptenable register: bit description bit symbol description 31 mie masterinterruptenable by the hcd: logic 0 is ignored by the hc. logic 1 enables interrupt generation by events speci ed in other bits of this register. 30 to 7 - reserved 6 rhsc 0 ignore 1 enable interrupt generation because of root hub status change 5 fno 0 ignore 1 enable interrupt generation because of frame number over ow 4ue 0 ignore 1 enable interrupt generation because of unrecoverable error 3rd 0 ignore 1 enable interrupt generation because of resume detect 2sf 0 ignore 1 enable interrupt generation because of start of frame 1 - reserved 0so 0 ignore 1 enable interrupt generation because of scheduling overrun
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 77 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. writing logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. ta b l e 4 5 provides the bit allocation of the hcinterruptdisable register. code (hex): 05 read code (hex): 85 write table 45: hcinterruptdisable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w table 46: hcinterruptdisable register: bit description bit symbol description 31 mie logic 0 is ignored by the hc. logic 1 disables interrupt generation because of events speci ed in other bits of this register. this eld is set after a hardware or software reset. 30 to 7 - reserved 6 rhsc 0 ignore 1 disable interrupt generation because of root hub status change 5 fno 0 ignore 1 disable interrupt generation because of frame number over ow 4ue 0 ignore 1 disable interrupt generation because of unrecoverable error 3rd 0 ignore 1 disable interrupt generation because of resume detect
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 78 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.2 hc frame counter registers 15.2.1 hcfminterval register (r/w: 0dh/8dh) the hcfminterval register (bit allocation: ta b l e 4 7 ) contains a 14-bit value that indicates the bit time interval in a frame between two consecutive sofs. in addition, it contains a 15-bit value indicating the full-speed maximum packet size that the hc may transmit or receive without causing a scheduling overrun. the hcd may carry out minor adjustments on frameinterval by writing a new value over the present one at each sof. this provides the programmability necessary for the hc to synchronize with an external clocking resource and to adjust any unknown local clock offset. code (hex): 0d read code (hex): 8d write 2sf 0 ignore 1 disable interrupt generation because of start of frame 1 - reserved 0so 0 ignore 1 disable interrupt generation because of scheduling overrun table 46: hcinterruptdisable register: bit description continued bit symbol description table 47: hcfminterval register: bit allocation bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved fi[13:8] reset - - 101110 access - - r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset 11011111 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 79 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.2.2 hcfmremaining register (r/w: 0eh/8eh) the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. the bit allocation is given in ta b l e 4 9 . code (hex): 0e read code (hex): 8e write table 48: hcfminterval register: bit description bit symbol description 31 fit frameintervaltoggle: the hcd toggles this bit whenever it loads a new value to frameinterval. 30 to 16 fsmps [14:0] fslargestdatapacket: speci es a value that is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits that can be sent or received by the hc in a single transaction at any given time without causing a scheduling overrun. the eld value is calculated by the hcd. 15 to 14 - reserved 13 to 0 fi[13:0] frameinterval: speci es the interval between two consecutive sofs in bit times. the nominal value is set to 11999. the hcd must store the current value of this eld before resetting the hc. setting the hostcontrollerreset (hcr) eld of the hccommandstatus register causes the hc to reset this eld to its nominal value. the hcd may choose to restore the stored value upon completing the reset sequence. table 49: hcfmremaining register: bit allocation bit 31 30 29 28 27 26 25 24 symbol frt reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved fr[13:8] reset - - 000000 access - - r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 80 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.2.3 hcfmnumber register (r/w: 0fh/8fh) the hcfmnumber register is a 16-bit counter, and the bit allocation is given in ta b l e 5 1 . it provides a timing reference for events happening in the hc and the hcd. the hcd may use the 16-bit value speci ed in this register and generate a 32-bit frame number without requiring frequent access to the register. code (hex): 0f read code (hex): 8f write table 50: hcfmremaining register: bit description bit symbol description 31 frt frameremainingtoggle: this bit is loaded from the frameintervaltoggle (fit) eld of hcfminterval whenever frameremaining (fr) reaches 0. this bit is used by the hcd for synchronization between frameinterval (fi) and frameremaining (fr). 30 to 14 - reserved 13 to 0 fr[13:0] frameremaining: this counter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterval (fi) value speci ed in hcfminterval at the next bit time boundary. when entering the usboperational state, the hc reloads it with the content of the frameinterval (fi) part of the hcfminterval register and uses the updated value from the next sof. table 51: hcfmnumber register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol fn[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00000000 access rrrrrrrr
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 81 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.2.4 hclsthreshold register (r/w: 11h/91h) the hclsthreshold register contains an 11-bit value used by the hc to determine whether to commit to the transfer of a maximum of 8-byte ls packet before the eof. neither the hc nor the hcd is allowed to change this value. ta b l e 5 3 shows the bit allocation of the register. code (hex): 11 read code (hex): 91 write table 52: hcfmnumber register: bit description bit symbol description 31 to 16 ? reserved 15 to 0 fn[15:0] framenumber: this is incremented when hcfmremaining is reloaded. it needs to be rolled over to 0h after ffffh. when the usboperational state is entered, this is incremented automatically. the content needs to be written to hcca after the hc has incremented the framenumber (fn) at each frame boundary and sent an sof. however, the content needs to be written before the hc reads the rst endpoint descriptor (ed) in that frame. after writing to hcca, the hc needs to set the startofframe (sf) in hcinterruptstatus. table 53: hclsthreshold register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved lst[10:8] reset -----110 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 00101000 access r/w r/w r/w r/w r/w r/w r/w r/w table 54: hclsthreshold register: bit description bit symbol description 31 to 11 ? reserved 10 to 0 lst[10:0] lsthreshold: contains a value that is compared to the frameremaining (fr) eld before a low-speed transaction is initiated. the transaction is started only if frameremaining (fr) this eld. the value is calculated by the hcd, which considers transmission and set-up overhead.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 82 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.3 hc root hub registers all registers included in this partition are dedicated to the usb root hub, which is an integral part of the hc although it is a functionally a separate entity. the hcd emulates usb driver (usbd) accesses to the root hub by using a register interface. the hcd maintains many usb-de ned hub features that are not required to be supported in hardware. for example, the hub s device, con guration, interface and endpoint descriptors are maintained only in the hcd, as well as some static elds of the class descriptor. the hcd also maintains and decodes the address of the root hub device and other trivial operations that are better suited to software than to hardware. root hub registers are developed to maintain the similarity of bit organization and operation to typical hubs found in the system. four registers are de ned as follows: hcrhdescriptora hcrhdescriptorb hcrhstatus hcrhportstatus[1:ndp]. each register is read and written as a dword. these registers are only written during initialization to correspond with the system implementation. the hcrhdescriptora and hcrhdescriptorb registers should be implemented such that they are writeable, regardless of the usb states of the hc. hcrhstatus and hcrhportstatus must be writeable during the usboperational state. 15.3.1 hcrhdescriptora register (r/w: 12h/92h) the hcrhdescriptora register is the rst register of two describing the characteristics of the root hub. the bit allocation is given in ta b l e 5 5 . code (hex): 12 read code (hex): 92 write table 55: hcrhdescriptora register: bit description bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset 11111111 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved nocp ocpm dt nps psm reset - - - 01001 access - - - r/w r/w r r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 83 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 7 6 5 4 3 2 1 0 symbol reserved ndp[1:0] reset ------10 access ------rr table 56: hcrhdescriptora register: bit description bit symbol description 31 to 24 potpgt [7:0] powerontopowergoodtime: this byte speci es the duration hcd has to wait before accessing a powered-on port of the root hub. it is implementation-speci c (is). the unit of time is 2 ms. the duration is calculated as potpgt 2ms. 23 to 13 - reserved 12 nocp noovercurrentprotection: this bit describes how the overcurrent status for the root hub ports are reported. when this bit is cleared, the overcurrentprotectionmode (ocpm) eld speci es global or per-port reporting. 0 overcurrent status is collectively reported for all downstream ports 1 no overcurrent reporting supported 11 ocpm overcurrentprotectionmode: this bit describes how the overcurrent status for the root hub ports are reported. at reset, this eld should re ect the same mode as powerswitchingmode. this eld is valid only if the noovercurrentprotection (nocp) eld is cleared. 0 overcurrent status is reported collectively for all downstream ports 1 overcurrent status is reported on a per-port basis. on power up, clear this bit and then set it to logic 1 10 dt devicetype: this bit speci es that the root hub is not a compound device; it is not permitted. this eld should always read as 0. 9 nps nopowerswitching: this bit is used to specify whether power switching is supported or ports are always powered. it is implementation speci c. when this bit is cleared, the powerswitchingmode (psm) bit speci es global or per-port switching. 0 ports are power switched 1 ports are always powered on when the hc is powered on
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 84 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.3.2 hcrhdescriptorb register (r/w: 13h/93h) the hcrhdescriptorb register is the second register of two describing the characteristics of the root hub. these elds are written during initialization to correspond with the system implementation. reset values are implementation speci c. ta b l e 5 7 shows the bit allocation of the register. code (hex): 13 read code (hex): 93 write 8 psm powerswitchingmode: this bit is used to specify how the power switching of the root hub ports is controlled. it is implementation speci c. this eld is valid only if the nopowerswitching (nps) eld is cleared. 0 all ports are powered at the same time 1 each port is individually powered. this mode allows port power to be controlled by either the global switch or per-port switching. if the portpowercontrolmask (ppcm) bit is set, the port responds to only port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7 to 2 - reserved 1 to 0 ndp[1:0] numberdownstreamports: these bits specify the number of downstream ports supported by the root hub. it is implementation speci c. the maximum number of ports supported is 2. table 56: hcrhdescriptora register: bit description continued bit symbol description table 57: hcrhdescriptorb register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved ppcm[2:0] reset ----- is access -----r/wr/wr/w bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved dr[2:0] reset ----- is access -----r/wr/wr/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 85 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.3.3 hcrhstatus register (r/w: 14h/94h) the hcrhstatus register is divided into two parts. the lower word of a dword represents the hub status eld and the upper word represents the hub status change eld. reserved bits should always be written as logic 0. see ta b l e 5 9 for bit allocation of the register. code (hex): 14 read code (hex): 94 write table 58: hcrhdescriptorb register: bit description bit symbol description 31 to 19 - reserved 18 to 16 ppcm[2:0] portpowercontrolmask: each bit indicates whether a port is affected by a global power control command when powerswitchingmode is set. when set, the power state of the port is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is con gured to global switching mode (powerswitchingmode = 0), this eld is not valid. bit 2 ganged-power mask on port 2 bit 1 ganged-power mask on port 1 bit 0 reserved 15 to 3 - reserved 2 to 0 dr[2:0] deviceremovable: each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 2 device attached to port 2 bit 1 device attached to port 1 bit 0 reserved table 59: hcrhstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol crwe reserved reset 0------- access w------- bit 23 22 21 20 19 18 17 16 symbol reserved ccic lpsc reset ------00 access ------r/wr/w bit 15 14 13 12 11 10 9 8 symbol drwe reserved reset 0------- access r/w-------
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 86 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 7 6 5 4 3 2 1 0 symbol reserved oci lps reset ------00 access ------rr/w table 60: hcrhstatus register: bit description bit symbol description 31 crwe on write clearremotewakeupenable: writing logic 1 clears deviceremovewakeupenable (drwe). writing logic 0 has no effect. 30 to 18 - reserved 17 ccic overcurrentindicatorchange: this bit is set by hardware when a change has occurred to the overcurrentindicator (oci) eld of this register. the hcd clears this bit by writing logic 1. writing logic 0 has no effect. 16 lpsc on read localpowerstatuschange: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write setglobalpower: in the global power mode (powerswitchingmode = 0), logic 1 is written to this bit to turn on power to all ports (clear portpowerstatus). in the per-port power mode, it sets portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing logic 0 has no effect. 15 drwe on read deviceremotewakeupenable: this bit enables the bit connectstatuschange as a resume event, causing a state transition from usbsuspend to usbresume and setting the resumedetected interrupt. 0 connectstatuschange is not a remote wake-up event 1 connectstatuschange is a remote wake-up event on write setremotewakeupenable: writing logic 1 sets deviceremovewakeupenable. writing logic 0 has no effect. 14 to 2 - reserved 1 oci overcurrentindicator: this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when cleared, all power operations are normal. if per-port overcurrent protection is implemented, this bit is always logic 0. 0 lps on read localpowerstatus: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clearglobalpower: in the global power mode (powerswitchingmode = 0), logic 1 is written to this bit to turn off power to all ports (clear portpowerstatus). in the per-port power mode, it clears portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing logic 0 has no effect.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 87 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.3.4 hcrhportstatus[1:2] register (r/w [1]: 15h/95h; [2]: 16h/96h) the hcrhportstatus[1:2] register is used to control and report port events on a per-port basis. numberdownstreamports represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to re ect the port status, whereas the upper word re ects the status change bits. some status bits are implemented with special write behavior. if a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written logic 0. the bit allocation of the hcrhportstatus[1:2] register is given in ta b l e 6 1 . code (hex): [1] = 15, [2] = 16 read code (hex): [1] = 95, [2] = 96 write table 61: hcrhportstatus[1:2] register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved prsc ocic pssc pesc csc reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lsda pps reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol reserved prs poci pss pes ccs reset - - - 00000 access - - - r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 88 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 62: hcrhportstatus[1:2] register: bit description bit symbol description 31 to 21 - reserved 20 prsc portresetstatuschange: this bit is set at the end of the 10 ms port reset signal. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 port reset is not complete 1 port reset is complete 19 ocic portovercurrentindicatorchange: this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when the root hub changes the portovercurrentindicator (poci) bit. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in portovercurrentindicator (poci) 1 portovercurrentindicator (poci) has changed 18 pssc portsuspendstatuschange: this bit is set when the full resume sequence is complete. this sequence includes the 20 ms resume pulse, ls eop and 3 ms re-synchronization delay. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. this bit is also cleared when resetstatuschange is set. 0 resume is not completed 1 resume is completed 17 pesc portenablestatuschange: this bit is set when hardware events cause the portenablestatus (pes) bit to be cleared. changes from the hcd writes do not set this bit. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in portenablestatus (pes) 1 change in portenablestatus (pes) 16 csc connectstatuschange: this bit is set whenever a connect or disconnect event occurs. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared when a setportreset, setportenable or setportsuspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes should not occur if the port is disconnected. 0 no change in currentconnectstatus (ccs) 1 change in currentconnectstatus (ccs) remark: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 - reserved
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 89 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9 lsda on read lowspeeddeviceattached: this bit indicates the speed of the device attached to this port. when set, a low-speed device is attached to this port. when cleared, a full-speed device is attached to this port. this eld is valid only when currentconnectstatus (ccs) is set. 0 full-speed device attached 1 low-speed device attached on write clearportpower: the hcd clears the portpowerstatus (pps) bit by writing logic 1 to this bit. writing logic 0 has no effect. 8 pps on read portpowerstatus: this bit re ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd sets this bit by writing setportpower or setglobalpower. the hcd clears this bit by writing clearportpower or clearglobalpower. powerswitchingmode (pcm) and portpowercontrolmask[ndp] (ppcm[ndp]) determine which power control switches are enabled. in the global switching mode (powerswitchingmode = 0), only the set/clearglobalpower command controls this bit. in the per-port power switching (powerswitchingmode = 1), if the portpowercontrolmask[ndp] (ppcm[ndp]) bit for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnectstatus (ccs), portenablestatus (pes), portsuspendstatus (pss) and portresetstatus (prs) should be reset. 0 port power is off 1 port power is on on write setportpower: the hcd writes logic 1 to set the portpowerstatus (pps) bit. writing logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved table 62: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 90 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4 prs on read portresetstatus: when this bit is set by a write to setportreset, port reset signaling is asserted. when reset is completed, this bit is cleared when portresetstatuschange (prsc) is set. this bit cannot be set if currentconnectstatus (ccs) is cleared. 0 port reset signal is not active 1 port reset signal is active on write setportreset: the hcd sets the port reset signaling by writing logic 1 to this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portresetstatus (prs) but instead sets connectstatuschange (csc). this informs the driver that it attempted to reset a disconnected port. 3 poci on read portovercurrentindicator: this bit is valid only when the root hub is con gured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always re ects the overcurrent input signal 0 no overcurrent condition 1 overcurrent condition detected on write clearsuspendstatus: the hcd writes logic 1 to initiate a resume. writing logic 0 has no effect. a resume is initiated only if portsuspendstatus (pss) is set. table 62: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 91 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2 pss on read portsuspendstatus: this bit indicates whether the port is suspended or is in the resume sequence. it is set by a setsuspendstate write and cleared when portsuspendstatuschange (pssc) is set at the end of the resume interval. this bit cannot be set if currentconnectstatus (ccs) is cleared. this bit is also cleared when portresetstatuschange (prsc) is set at the end of the port reset or when the hc is placed in the usbresume state. if an upstream resume is in progress, it should propagate to the hc. 0 port is not suspended 1 port is suspended on write setportsuspend: the hcd sets the portsuspendstatus (pss) bit by writing logic 1 to this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portsuspendstatus (pss); instead it sets connectstatuschange (csc). this informs the driver that it attempted to suspend a disconnected port. 1 pes on read portenablestatus: this bit indicates whether the port is enabled or disabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error, such as babble, is detected. this change also causes portenablestatuschange to be set. the hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus (ccs) is cleared. this bit is also set, if it is not already, at the completion of a port reset when resetstatuschange is set or port suspend when suspendstatuschange is set. 0 port is disabled 1 port is enabled on write setportenable: the hcd sets portenablestatus (pes) by writing logic 1. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portenablestatus (pes), but instead sets connectstatuschange (csc). this informs the driver that it attempted to enable a disconnected port. 0 ccs on read currentconnectstatus: this bit re ects the current state of the downstream port. 0 no device connected 1 device connected on write clearportenable: the hcd writes logic 1 to this bit to clear the portenablestatus (pes) bit. writing logic 0 has no effect. currentconnectstatus (csc) is not affected by any write. remark: this bit always reads 1b when the attached device is nonremovable (deviceremovable[ndp]). table 62: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 92 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.4 hc dma and interrupt control registers 15.4.1 hchardwarecon guration register (r/w: 20h/a0h) the bit allocation of the hchardwarecon guration register is given in ta b l e 6 3 . code (hex): 20 read code (hex): a0 write table 63: hchardwarecon guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol disable suspend_ wakeup global power down connect pulldown _ds2 connect pulldown _ds1 suspend clknotstop analogoc enable oneint dackmode reset 00000 000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol onedma dackinput polarity dreq output polarity databuswidth[1:0] interrupt output polarity interrupt pintrigger interruptpin enable reset 00101 000 access r/w r/w r/w r/w r/w r/w r/w r/w table 64: hchardwarecon guration register: bit description bit symbol description 15 disablesuspend_wakeup this bit when set to logic 1 disables the function of the d_suspend/ d_w akeup and h_suspend/ h_w akeup pins. therefore, these pins will always remain high and pulling them low does not wake up the hc and the dc. 14 globalpowerdown set this bit to logic 1 to reduce power consumption of the otg atx in the suspend mode. 13 connectpulldown_ds2 0 disconnect built-in pull-down resistors on h_dm2 and h_dp2 1 connect built-in pull-down resistors on h_dm2 and h_dp2 for the downstream port 2 remark: port 2 is always used as a host port.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 93 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12 connectpulldown_ds1 0 disconnect built-in pull-down resistors on otg_dm1 and otg_dp1 1 connect built-in pull-down resistors on otg_dm1 and otg_dp1 remark: this bit is effective only when port 1 is con gured as the host port (the o tgmode pin is high, and the id pin is low). when port 1 is con gured as the otg port, (the o tgmode pin is low), the pull-down resistors on otg_dm1 and otg_dp1 are controlled by the loc_pull_dn_dp and loc_pull_dn_dm bits of the otgcontrol register. 11 suspendclknotstop 0 clock can be stopped when suspended 1 clock cannot be stopped when suspended 10 analogocenable 0 use external oc detection; digital input 1 use on-chip oc detection; analog input 9 oneint 0 hc interrupt routed to int1, dc interrupt routed to int2 1 hc and dc interrupts routed to int1 only, int2 is unused 8 dackmode 0 normal operation; d a ck1 is used with read and write signals; power-up value 1 reserved 7 onedma 0 hc dma request and acknowledge routed to dreq1 and d a ck1, dc dma request and acknowledge routed to dreq2 and d a ck2 1 hc and dc dma requests and acknowledges routed to dreq1 and d a ck1; dreq2 and d a ck2 unused 6 dackinputpolarity 0 d a ck1 is active low; power-up value 1 d a ck1 is active high 5 dreqoutputpolarity 0 dreq1 is active low 1 dreq1 is active high; power-up value 4 to 3 databuswidth[1:0] 01 microprocessor interface data bus width is 16 bits others reserved 2 interruptoutputpolarity 0 int1 interrupt is active low; power-up value 1 int1 interrupt is active high 1 interruptpintrigger 0 int1 interrupt is level-triggered; power-up value 1 int1 interrupt is edge-triggered 0 interruptpinenable 0 power-up value 1 global interrupt pin int1 is enabled; this bit should be used with the hc pinterruptenable register to enable pin int1 table 64: hchardwarecon guration register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 94 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.4.2 hcdmacon guration register (r/w: 21h/a1h) ta b l e 6 5 contains the bit allocation of the hcdmacon guration register. code (hex): 21 read code (hex): a1 write table 65: hcdmacon guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol dmacounter enable burstlen[1:0] dma enable buffer_type_select[2:0] dmaread writeselect reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 66: hcdmacon guration register: bit description bit symbol description 15 to 8 - reserved 7 dmacounterenable 0 reserved 1 dma counter is enabled. once the counter is enabled, the hcd must initialize the hctransfercounter register to a non-zero value for dreq to be raised after the dmaenable bit is set to high. 6 to 5 burstlen[1:0] 00 single-cycle burst dma 01 4-cycle burst dma 10 8-cycle burst dma 11 reserved i/o bus with 32-bit data path width supports only single and four cycle dma burst. 4 dmaenable 0 dma is disabled 1 dma is enabled this bit needs to be reset when the dma transfer is completed. 3 to 1 buffer_type_select [2:0] bit 3 bit 2 bit 1 buffer type 0 0 0 istl0 (default) 0 0 1 istl1 0 1 0 intl 011atl 1 x x direct addressing 0 dmareadwriteselect 0 read from the buffer memory of the hc 1 write to the buffer memory of the hc
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 95 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.4.3 hctransfercounter register (r/w: 22h/a2h) regardless of the programmed i/o (pio) or dma data transfer modes, this register is used to initialize the number of bytes to be transferred to or from the istl, intl or atl buffer ram. for the count value loaded in the register to take effect, the hcd is required to set bit 7 of the hcdmacon guration register to high. when the count value has reached, the hc needs to generate an internal eot signal to set bit 2 of the hc pinterrupt register, alleointerrupt, and update the hcbufferstatus register. the bit allocation of the hctransfercounter register is given in ta b l e 6 7 . code (hex): 22 read code (hex): a2 write 15.4.4 hc pinterrupt register (r/w: 24h/a4h) all the bits in this register are active at power-on reset. none of the active bits, however, will cause an interrupt on the interrupt pin (int1) unless they are set by the respective bits in the hc pinterruptenable register and bit 0 of the hchardwarecon guration register is also set. after this register (24h read) is read, the bits that are active will not be reset until logic 1 is written to the bits in this register (a4h write) to clear it. the bits in this register are cleared only when you write to this register indicating the bits to be cleared. to clear all the enabled bits in this register, the hcd must write ffh to this register. the bit allocation of the hc pinterrupt register is given in ta b l e 6 8 . code (hex): 24 read code (hex): a4 write table 67: hctransfercounter register: bit description bit symbol access value description 15 to 0 countervalue [15:0] r/w 0000h number of data bytes to be read from or written to the buffer ram. table 68: hc pinterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_irq atl_irq reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol intl_irq clkready hc suspended opr_reg alleot interrupt istl_1_ int istl_0_ int sof_int reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 96 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 69: hc pinterrupt register: bit description bit symbol description 15 to 10 - reserved 9 otg_irq 0 no event 1 the otg interrupt event needs to read the otginterrupt register to get the cause of the interrupt. 8 atl_irq 0 no event 1 count value of the hcatldonethresholdcount register or the time-out value of the hcatlptddonethresholdtimeout register has reached. the microprocessor is required to read hcintlptddonemap to check the ptds that have completed their transactions. 7 intl_irq 0 no event 1 the hc has detected the last ptd, and there is at least one interrupt transaction that has received ack from the device. the microprocessor is required to read hcintlptddonemap to check the ptds that have received ack from the device. 6 clkready 0 no event 1 the hc has awakened from the suspend state, and its internal clock has turned on again. 5hc suspended 0 no event 1 the hc has been suspended and no usb activities are sent from the microprocessor for each ms. the microprocessor can suspend the hc by setting bits 6 and 7 of the hccontrol register to logic 1. once the hc is suspended, no sof needs to be sent to the devices connected to downstream ports. 4 opr_reg 0 no event 1 an hc operation has caused a hardware interrupt. it is necessary for the hcd to read the hcinterruptstatus register to determine the cause of the interrupt. 3 alleot interrupt 0 no event 1 data transfer has been completed by using the pio transfer or the dma transfer. this bit is set either when the value of the hctransfercounter register has reached zero, or the eot pin of the hc is triggered by an external signal.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 97 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.4.5 hc pinterruptenable register (r/w: 25h/a5h) the bits 9:0 in this register are the same as those in the hc pinterrupt register. the bits in this register are used together with bit 0 of the hchardwarecon guration register to enable or disable the bits in the hc pinterrupt register. at power-on, all the bits in this register are masked with logic 0. this means no interrupt request output on the interrupt pin int1 can be generated. when a bit is set to logic 1, the interrupt for that bit is enabled. the bit allocation of the register is given in ta b l e 7 0 . code (hex): 25 read code (hex): a5 write 2 istl_1_ int 0 no event 1 the transaction of the last ptd stored on the istl1 buffer has been completed. the microprocessor is required to read data from the istl1 buffer. the hcd must rst read the hcbufferstatus register to check the status of the istl1 buffer before reading data to the microprocessor. 1 istl_0_ int 0 no event 1 the transaction of the last ptd stored on the istl0 buffer has been completed. the microprocessor is required to read data from the istl0 buffer. the hcd must rst read the hcbufferstatus register to check the status of the istl0 buffer before reading data to the microprocessor. 0 sof_int 0 no event 1 the hc is in the sof state and it indicates the start of a new frame. the hcd must rst read the hcbufferstatus register to check the status of the istl buffer before reading data to the microprocessor. for the microprocessor to perform the dma transfer of iso data from or to the istl buffer, the hc must rst initialize the hcdmacon guration register. table 69: hc pinterrupt register: bit description continued bit symbol description table 70: hc pinterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_irq_ interrupt enable atl_irq_ interrupt enable reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol intl_irq_ interrupt enable clkready hc suspended enable opr interrupt enable eot interrupt enable istl_1 interrupt enable istl_0 interrupt enable sof interrupt enable reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 98 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.5 hc miscellaneous registers 15.5.1 hcchipid register (r: 27h) this register contains the id of the isp1362. the upper byte identi es the product name (here 36h stands for the isp1362). the lower byte indicates the revision number of the product including engineering samples. ta b l e 7 2 contains the bit description of the register. code (hex): 27 read only 15.5.2 hcscratch register (r/w: 28h/a8h) this register is for the hcd to save and restore values when required. the bit description is given in ta b l e 7 3 . code (hex): 28 read code (hex): a8 write table 71: hc pinterruptenable register: bit description bit symbol description 15 to 10 - reserved 9 otg_irq_ interruptenable 0 power-up value 1 enables the otg_irq interrupt 8 atl_irq_ interruptenable 0 power-up value 1 enables the atl_irq interrupt 7 intl_irq_ interruptenable 0 power-up value 1 enables the int_irq interrupt 6 clkready 0 power-up value 1 enables the clkready interrupt 5 hcsuspendedenable 0 power-up value 1 enables the hc suspended interrupt 4 oprinterruptenable 0 power-up value 1 enables the 32-bit operational register s interrupt 3 eotinterruptenable 0 power-up value 1 enables the eot interrupt 2 istl_1interrupt enable 0 power-up value 1 enables the istl_1 interrupt 1 istl_0interrupt enable 0 power-up value 1 enables the istl_0 interrupt 0 sofinterrupt enable 0 power-up value 1 enables the sof interrupt table 72: hcchipid register: bit description bit symbol access value description 15 to 0 chipid[15:0] r 3630h chip id of the isp1362.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 99 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.5.3 hcsoftwarereset register (w: a9h) this register provides a means for software reset of the hc. to reset the hc, the hcd must write a reset value of f6h to this register. on receiving this reset value, the hc resets all the hc and otg registers, except its buffer memory. ta b l e 7 4 contains the bit description of the register. code (hex): a9 write only 15.6 hc buffer ram control registers 15.6.1 hcbufferstatus register (r/w: 2ch/ach) the bit allocation of the hcbufferstatus register is given in ta b l e 7 5 . code (hex): 2c read code (hex): ac write table 73: hcscratch register: bit description bit symbol access value description 15 to 0 scratch[15:0] r/w 0000h scratch register value. table 74: hcsoftwarereset register: bit description bit symbol access value description 15 to 0 resetvalue [15:0] w 0000h writing a reset value of f6h causes the hc to reset all the registers except its buffer memory. table 75: hcbufferstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved pairedptd pingpong istl1 bufferdone istl0 bufferdone reset -----000 access -----rrr bit 7 6 5 4 3 2 1 0 symbol reserved istl1_ active status istl0_ active status reset_hw pingpong reg atl_active intl_ active istl1 bufferfull istl0 bufferfull reset - 0000000 access - r r r/w r/w r/w r/w r/w table 76: hcbufferstatus register: bit description bit symbol description 15 to 11 - reserved 10 pairedptdpingpong 0 ping of paired ptd in atl is active. 1 pong of paired ptd in atl is active. 9 istl1 bufferdone 0 the istl1 buffer has not yet been read by the hc. 1 the istl1 buffer has been read by the hc. 8 istl0 bufferdone 0 the istl0 buffer has not yet been read by the hc. 1 the istl0 buffer has been read by the hc.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 100 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.6.2 hcdirectaddresslength register (r/w: 32h/b2h) the hcdirectaddresslength register is used for direct addressing of the istl, intl or atl buffers. this register speci es the starting address of the buffer and byte count of the data to be addressed. therefore, it allows the programmer to randomly access the buffer. the bit allocation of the register is given in ta b l e 7 7 . code (hex): 32 read code (hex): b2 write 7 - reserved 6 istl1_activestatus 0 the istl1 buffer is not accessed by the slave host. 1 the istl1 buffer is accessed by the slave host. 5 istl0_activestatus 0 the istl0 buffer is not accessed by the slave host. 1 the istl0 buffer is accessed by the slave host. 4 reset_hw pingpong reg 0to1 resets internal hardware ping pong register to 0 when atl_active is 0. the hardware ping pong register can be read from bit 10 of this register. 1to0 has no effect. 3 atl_active 0 the hc does not process the atl buffer. 1 the hc processes the atl buffer. 2 intl_active 0 the hc does not process the intl buffer. 1 the hc processes the intl buffer. 1 istl1bufferfull 0 the hc does not process the istl1 buffer. 1 the hc processes the istl1 buffer. 0 istl0bufferfull 0 the hc does not process the istl0 buffer. 1 the hc processes the istl0 buffer. table 76: hcbufferstatus register: bit description continued bit symbol description table 77: hcdirectaddresslength register: bit allocation bit 31 30 29 28 27 26 25 24 symbol databytecount[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol databytecount[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved bufferstartaddress[14:8] reset 00000000 access - r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 101 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.6.3 hcdirectaddressdata register (r/w: 45h/c5h) this is a data port for the hcd to access the istl, intl or atl buffers under the direct addressing mode. ta b l e 7 9 contains the bit description of the register. code (hex): 45 read code (hex): c5 write 15.7 isochronous (iso) transfer registers 15.7.1 hcistlbuffersize register (r/w: 30h/b0h) this register requires you to allocate the size of the buffer to be used for iso transactions. the buffer size speci ed in the register is applied to the istl0 and istl1 buffers. therefore, istl0 and istl1 always have the same buffer size. ta b l e 8 0 shows the bit description of the register. code (hex): 30 read code (hex): b0 write 15.7.2 hcistl0bufferport register (r/w: 40h/c0h) in addition to the hcdirectaddressdata register, the isp1362 provides this register to act as another data port for accessing the istl0 buffer. the starting address for accessing the buffer is always xed at 0000h. therefore, random access of the istl0 buffer is not allowed. the bit description of the register is given in ta b l e 8 1 . bit 7 6 5 4 3 2 1 0 symbol bufferstartaddress[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 78: hcdirectaddresslength register: bit description bit symbol description 31 to 16 databytecount [15:0] total number of bytes to be accessed. 15 - reserved 14 to 0 bufferstartaddress[14:0] the starting address of the buffer for accessing of data. table 79: hcdirectaddressdata register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data port for accessing the istl, intl or atl buffers. the address of the buffer and byte count of the data must be speci ed in the hcdirectaddresslength register. table 80: hcistlbuffersize register: bit description bit symbol access value description 15 to 0 istlbuffer size[15:0] r/w 0000h the size of the buffer to be used for iso transactions and must be speci ed in bytes.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 102 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): 40 read code (hex): c0 write the hcd is rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (40h for reading from the istl0 buffer, and c0h for writing to the istl0 buffer) to the hc through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the istl0 buffer or writing data to the istl0 buffer. while the hcd is accessing the buffer, the buffer pointer of istl0 also increases automatically. when the pointer has reached the initialized byte count of the hctransfercounter register, the hc sets the alleotinterrupt bit of the hc pinterrupt register to logic 1 and updates the hcbufferstatus register. 15.7.3 hcistl1bufferport register (r/w: 42h/c2h) in addition to the hcdirectaddressdata register, the isp1362 provides this register to act as another data port for accessing the istl1 buffer. the starting address for accessing the buffer is always xed at 0000h. therefore, random access of the istl1 buffer is not allowed. the bit description of the register is given in ta b l e 8 2 . code (hex): 42 read code (hex): c2 write the hcd is rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (42h for reading from the istl1 buffer, and c2h for writing to the istl1 buffer) to the hc through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the istl1 buffer or writing data to the istl1 buffer. while the hcd is accessing the buffer, the buffer pointer of istl1 also increases automatically. when the pointer has reached the initialized byte count of the hctransfercounter register, the hc sets the alleotinterrupt bit in the hc pinterrupt register to logic 1 and updates the hcbufferstatus register. 15.7.4 hcistltogglerate register (r/w: 47h/c7h) the rate of toggling between istl0 and istl1 is programmable. the hcistltogglerate register is provided for programming the required toggle rate in the range of 0 ms to 15 ms at intervals of 1 ms. the bit allocation of the register is shown in ta b l e 8 3 . code (hex): 47 read code (hex): c7 write table 81: hcistl0bufferport register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data in the istl0 buffer to be accessed through this data port. table 82: hcistl1bufferport register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data in the istl1 buffer to be accessed through this data port.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 103 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.8 interrupt transfer registers 15.8.1 hcintlbuffersize register (r/w: 33h/b3h) this register allows you to allocate the size of the intl buffer to be used for interrupt transactions. the default value of the buffer size is set to 128 bytes, and the maximum allowable allocated size is 4096 bytes. ta b l e 8 5 shows the bit description of the register. code (hex): 33 read code (hex): b3 write 15.8.2 hcintlbufferport register (r/w: 43h/c3h) in addition to the hcdirectaddressdata register, the isp1362 provides this register to act as another data port for accessing the intl buffer. the starting address for accessing the buffer is always xed at 0000h. therefore, random access of the intl buffer is not allowed. the bit description of the hcintlbufferport register is given in ta b l e 8 6 . code (hex): 43 read code (hex): c3 write table 83: hcistltogglerate register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved istltogglerate[3:0] reset ---- 0000 access ----r/wr/wr/wr/w table 84: hcistltogglerate register: bit description bit symbol description 15 to 4 - reserved 3 to 0 istltogglerate[3:0] the required toggle rate in ms. table 85: hcintlbuffersize register: bit description bit symbol access value description 15 to 0 intlbuffer size[15:0] r/w 0080h the size of the buffer to be used for interrupt transactions and must be speci ed in bytes. table 86: hcintlbufferport register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data in the intl buffer to be accessed through this data port.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 104 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hcd is rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (43h for reading of the intl buffer, and c3h for writing to the intl buffer) to the hc through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the intl buffer or writing data to the intl buffer. while the hcd is accessing the buffer, the buffer pointer of intl also increases automatically. when the pointer has reached the initialized byte count of the hctransfercounter register, the hc sets the alleotinterrupt bit of the hc pinterrupt register to logic 1 and updates the hcbufferstatus register. 15.8.3 hcintlblksize register (r/w: 53h/d3h) the isp1362 requires the intl buffer to be partitioned into several equal sized blocks so that the hc can skip the current ptd and proceed to process the next ptd easily. the block size of the intl buffer is required to be speci ed in this register and must be a multiple of 8 bytes. the default value of the block size is 64 bytes, and the maximum allowable block size is 1024 bytes. ta b l e 8 7 shows the bit allocation of the register. code (hex): 53 read code (hex): d3 write 15.8.4 hcintlptddonemap register (r: 17h) this is a 32-bit register, and the bit description is given in ta b l e 8 9 . every bit of the register represents the processing status of a ptd. bit 0 of the register represents the rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the register is updated once every ms by the hc and is cleared upon read by the hcd. bits that are set representing its corresponding ptds are processed by the hc and the ack token is received from the device. code (hex): 17 read only table 87: hcintlblksize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved blocksize[9:8] reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol blocksize[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 88: hcintlblksize register: bit description bit symbol description 15 to 10 - reserved 9 to 0 blocksize[9:0] the block size of the intl buffer.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 105 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.8.5 hcintlptdskipmap register (r/w: 18h/98h) this is a 32-bit register, and the bit description is given in ta b l e 9 0 . bit 0 of the register represents the rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. when a bit is set by the hcd, the corresponding ptd is skipped and is not processed by the hc. the hc processes the skipped ptd if the hcd has reset its corresponding skipped bit to logic 0. clearing the corresponding bit in the hcintlptdskipmap register when there is no valid data in the block will cause unpredictable behavior of the hc. code (hex): 18 read code (hex): 98 write 15.8.6 hcintllastptd register (r/w: 19h/99h) this is a 32-bit register, and ta b l e 9 1 shows its bit description. bit 0 of the register represents the rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the bit that is set to logic 1 by the hcd is used as an indication to the hc that its corresponding ptd is the last ptd stored in the intl buffer. when the processing of the last ptd is complete, the hc proceeds to process atl transactions. code (hex): 19 read code (hex): 99 write 15.8.7 hcintlcurrentactiveptd register (r: 1ah) this register indicates which ptd stored in the intl buffer is currently active and is updated by the hc. the hcd can use it as a buffer pointer to decide which ptd locations are currently free for lling in new ptds to the buffer. this indication is to prevent the hcd from accidentally writing into the currently active ptd buffer location. ta b l e 9 2 shows the bit allocation of the register. code (hex): 1a read only table 89: hcintlptddonemap register: bit description bit symbol access value description 31 to 0 ptddone bits[31:0] r 0000h 0 the ptd stored in the intl buffer has not been successfully processed by the hc. 1 the ptd stored in the intl buffer has been successfully processed by the hc. table 90: hcintlptdskipmap register: bit description bit symbol access value description 31 to 0 skipbits [31:0] r/w 0000h 0 the hc processes the ptd. 1 the hc skips processing the ptd. table 91: hcintllastptd register: bit description bit symbol acc ess value description 31 to 0 lastptd bits[31:0] r/w 0000h 0 the ptd is not the last ptd stored in the buffer. 1 the ptd is the last ptd stored in the buffer.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 106 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.9 control and bulk transfer (aperiodic transfer) registers 15.9.1 hcatlbuffersize register (r/w: 34h/b4h) this register allows you to allocate the size of the atl buffer to be used for aperiodic transactions. the default value of the buffer size is set to 512 bytes, and the maximum allowable allocated size is 4096 bytes. the bit description of the register is given in ta b l e 9 4 . code (hex): 34 read code (hex): b4 write 15.9.2 hcatlbufferport register (r/w: 44h/c4h) in addition to the hcdirectaddressdata register, the isp1362 provides this register to act as another data port for accessing the atl buffer. the starting address for accessing the buffer is always xed at 0000h. therefore, random access of the atl buffer is not allowed. the bit description of the hcatlbufferport register is given in ta b l e 9 5 . code (hex): 44 read code (hex): c4 write table 92: hcintlcurrentactiveptd register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved activeptd[4:0] reset - - - 00000 access - - - rrrrr table 93: hcintlcurrentactiveptd register: bit description bit symbol description 15 to 5 - reserved 4 to 0 activeptd[4:0] this 5-bit number represents the ptd that is currently active. table 94: hcatlbuffersize register: bit description bit symbol access value description 15 to 0 atlbuffer size[15:0] r/w 0200h the size of the buffer to be used for aperiodic transactions and must be speci ed in bytes. table 95: hcatlbufferport register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data of the atl buffer to be accessed through this data port.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 107 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hcd is rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (44h for reading from the atl buffer, and c4h for writing to the atl buffer) to the hc through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the atl buffer or writing data to the atl buffer. while the hcd is accessing the buffer, the buffer pointer of atl also increases automatically. when the pointer has reached the initialized byte count of the hctransfercounter register, the hc sets the alleotinterrupt bit of the hc pinterrupt register to logic 1 and updates the hcbufferstatus register. 15.9.3 hcatlblksize register (r/w: 54h/d4h) the isp1362 partitions the atl buffer into several equal sized blocks so that the hc can skip the current ptd and proceed to process the next ptd easily. the block size of the atl buffer must be speci ed in this register and must be a multiple of 8 bytes. the bit allocation of the hcatlblksize register is given in ta b l e 9 6 . code (hex): 54 read code (hex): d4 write 15.9.4 hcatlptddonemap register (r: 1bh) this is a 32-bit register. the bit description of the register is given in ta b l e 9 8 . every bit of the register represents the processing status of a ptd. bit 0 of the register represents the rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the register is immediately updated after the completion of each atl ptd processing. it is cleared upon reading by the hcd. bits that are set representing its corresponding ptds have been processed by the hc and ack token has been received from the device. code (hex): 1b read only table 96: hcatlblksize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved blocksize[9:8] reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol blocksize[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 97: hcatlblksize register: bit description bit symbol description 15 to 10 - reserved 9 to 0 blocksize[9:0] the block size of the atl buffer.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 108 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.9.5 hcatlptdskipmap register (r/w: 1ch/9ch) this is a 32-bit register, and the bit description is given in ta b l e 9 9 . bit 0 of the register represents the rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. when the bit is set by the hcd, the corresponding ptd is skipped and is not processed by the hc. the hc processes the skipped ptd only if the hcd has reset its corresponding skipped bit to logic 0. clearing the corresponding bit in the hcatlptdskipmap register when there is no valid data in the block will cause unpredictable behavior of the hc. code (hex): 1c read code (hex): 9c write 15.9.6 hcatllastptd register (r/w: 1dh/9dh) this is a 32-bit register. table 100 gives the bit description of the register. bit 0 of the register represents the rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the bit that is set to logic 1 by the hcd is used as an indication to the hc that its corresponding ptd is the last ptd stored in the atl buffer. when the processing of the last ptd is complete, the hc loops back to process the rst ptd stored in the buffer. code (hex): 1d read code (hex): 9d write 15.9.7 hcatlcurrentactiveptd register (r: 1eh) this register indicates which ptd stored in the atl buffer is currently active and is updated by the hc. the hcd can use it as a buffer pointer to decide which ptd locations are currently free for lling in new ptds to the buffer. this indication helps to prevent the hcd from accidentally writing into the currently active ptd buffer location. table 101 shows the bit allocation of the register. code (hex): 1e read only table 98: hcatlptddonemap register: bit description bit symbol access value description 31 to 0 ptddone bits[31:0] r 0000h 0 the ptd stored in the atl buffer was not successfully processed by the hc. 1 the ptd stored in the atl buffer was successfully processed by the hc. table 99: hcatlptdskipmap register: bit description bit symbol access value description 31 to 0 skipbits [31:0] r/w 0000h 0 the hc processes the ptd. 1 the hc skips processing the ptd. table 100: hcatllastptd register: bit description bit symbol access value description 31 to 0 lastptd bits[31:0] r/w 0000h 0 the ptd is not the last ptd stored in the buffer. 1 the ptd is the last ptd stored in the buffer.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 109 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.9.8 hcatlptddonethresholdcount register (r/w: 51h/d1h) this register speci es the number of atl ptd done required to trigger an atl ptddonecount. if set to 0x08, the hc would trigger the atl interrupt (in the hc pinterrupt register) once for every 8 atl ptd done. table 103 shows the bit allocation of the register. remark: do not write 0x0000 to this register. code (hex): 51 read code (hex): d1 write 15.9.9 hcatlptddonethresholdtimeout register (r/w: 52h/d2h) this register indicates the number of ms from the last time when the atl interrupt (in the hc pinterrupt register) was set, of which, if the number of atl ptddone is still less than hcatlptddonethresholdcount, the hc would trigger an atl interrupt (in table 101: hcatlcurrentactiveptd register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved activeptd[4:0] reset - - - 00000 access - - - rrrrr table 102: hcatlcurrentactiveptd register: bit description bit symbol description 15 to 5 - reserved 4 to 0 activeptd[4:0] this 5-bit number represents the ptd that is currently active. table 103: hcatlptddonethresholdcount register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved ptddonecount[4:0] reset - - - 00001 access - - - r/w r/w r/w r/w r/w table 104: hcatlptddonethresholdcount register: bit description bit symbol description 15 to 5 - reserved 4 to 0 ptddonecount[4:0] number of ptds processed by the hc.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 110 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hc pinterrupt register) to indicate a time-out situation, provided hcatlptddonemap is currently 0x0000 0000. table 105 shows the bit allocation of the hcatlptddone register. remark: if the time-out indication is not required by software, or there is no active ptd in the atl buffer, write 0x0000 to this register. code (hex): 52 read code (hex): d2 write 16. device controller (dc) registers the functions and registers of the dc are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in table 107 . a complete access consists of two phases: 1. command phase : when address pin a0 = high, the dc interprets the data on the lower byte of the bus (bits d7 to d0) as a command code. commands without a data phase are immediately executed. 2. data phase (optional) : when address pin a0 = low, the dc transfers the data on the bus to or from a register or endpoint buffer memory. in case of multi-byte registers, the least signi cant byte or word are accessed rst. the following applies to a register or buffer memory access in the 16-bit bus mode: the upper byte (bits d15 to d8) in the command phase or the unde ned byte in the data phase are ignored. the access of registers is word-aligned: byte access is not allowed. table 105: hcatlptddonethresholdtimeout register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol ptddonetimeout[7:0] reset 00000001 access r/w r/w r/w r/w r/w r/w r/w r/w table 106: hcatlptddonethresholdtimeout register: bit description bit symbol description 15 to 8 - reserved 7 to 0 ptddonetimeout[7:0] maximum allowable time in ms for the hc to retry a transaction with nak returned.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 111 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. if the packet length is odd, the upper byte of the last word in an in endpoint buffer is not transmitted to the host. when reading from an out endpoint buffer, the upper byte of the last word must be ignored by the rmware. the packet length is stored in the rst two bytes of the endpoint buffer. table 107: dc command and register summary name destination code (hex) transaction [1] initialization commands write control out con guration dcendpointcon guration register endpoint 0 out 20 write 1 byte [2] write control in con guration dcendpointcon guration register endpoint 0 in 21 write 1 byte [2] write endpoint n con guration (n = 1 to 14) dcendpointcon guration register endpoint 1 to 14 22 to 2f write 1 byte [2] read control out con guration dcendpointcon guration register endpoint 0 out 30 read 1 byte [2] read control in con guration dcendpointcon guration register endpoint 0 in 31 read 1 byte [2] read endpoint n con guration (n = 1 to 14) dcendpointcon guration register endpoint 1 to 14 32 to 3f read 1 byte [2] write or read device address dcaddress register b6/b7 write or read 1 byte [2] write or read mode register dcmode register b8/b9 write or read 1 byte [2] write or read hardware con guration dchardwarecon guration register ba/bb write or read 2 bytes write or read dcinterruptenable register dcinterruptenable register c2/c3 write or read 4 bytes write or read dma con guration dcdmacon guration register f0/f1 write or read 2 bytes write or read dma counter dcdmacounter register f2/f3 write or read 2 bytes reset device resets all registers f6 - data ow commands write control out buffer illegal: endpoint is read-only (00) - write control in buffer buffer memory endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt/bulk: n 64 bytes read control out buffer buffer memory endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) - read endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes [4] interrupt/bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoint 1 to 14 42 to 4f - read control out status dcendpointstatus register endpoint 0 out 50 read 1 byte [2] read control in status dcendpointstatus register endpoint 0 in 51 read 1 byte [2]
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 112 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] with n representing the number of bytes, the number of words for 16-bit bus width is: (n + 1) divided by 2. [2] when accessing an 8-bit register in the 16-bit mode, the upper byte is invalid. [3] validating an out endpoint buffer causes unpredictable behavior of the dc. [4] during the isochronous transfer in the 16-bit mode, because n 1023, the rmware must manage the upper byte. [5] clearing an in endpoint buffer causes unpredictable behavior of the dc. [6] reads a copy of the status register: executing this command does not clear any status bits or interrupt bits. read endpoint n status (n = 1 to 14) dcendpointstatus register n endpoint 1 to 14 52 to 5f read 1 byte [2] validate control out buffer illegal: in endpoints only [3] (60) - validate control in buffer buffer memory endpoint 0 in [3] 61 - validate endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (in endpoints only) [3] 62 to 6f - clear control out buffer buffer memory endpoint 0 out 70 - clear control in buffer illegal [5] (71) - clear endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (out endpoints only) [5] 72 to 7f unstall control out endpoint endpoint 0 out 80 - unstall control in endpoint endpoint 0 in 81 - unstall endpoint n (n = 1 to 14) endpoint 1 to 14 82 to 8f - check control out status [6] dcendpointstatusimage register endpoint 0 out d0 read 1 byte [2] check control in status [6] dcendpointstatusimage register endpoint 0 in d1 read 1 byte [2] check endpoint n status (n = 1 to 14) [6] dcendpointstatusimage register n endpoint 1 to 14 d2 to df read 1 byte [2] acknowledge set-up endpoint 0 in and out f4 - general commands read control out error code dcerrorcode register endpoint 0 out a0 read 1 byte [2] read control in error code dcerrorcode register endpoint 0 in a1 read 1 byte [2] read endpoint n error code (n = 1 to 14) dcerrorcode register endpoint 1 to 14 a2 to af read 1 byte [2] unlock device all registers with write access b0 write 2 bytes write or read dcscratch register dcscratch register b2/b3 write or read 2 bytes read frame number dcframenumber register b4 read 1 or 2 bytes read chip id dcchipid register b5 read 2 bytes read dcinterrupt register dcinterrupt register c0 read 4 bytes table 107: dc command and register summary continued name destination code (hex) transaction [1]
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 113 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con gure and enable the embedded endpoints. they also serve to set the usb assigned address of the dc and to perform a device reset. 16.1.1 dcendpointcon guration register (r/w: 30h 3fh/20h 2fh) this command is used to access the dcendpointcon guration register (ecr) of the target endpoint. it de nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), buffer memory size and buffering scheme. it also enables the endpoint buffer memory. the register bit allocation is shown in table 108 . a bus reset will disable all endpoints. the allocation of buffer memory only takes place after all 16 endpoints have been con gured in sequence (from endpoint 0 out to endpoint 14). although the control endpoints have xed con gurations, they must be included in the initialization sequence and must be con gured with their default values (see ta b l e 1 4 ). automatic buffer memory allocation starts when endpoint 14 has been con gured. remark: if any change is made to an endpoint con guration that affects the allocated memory (size, enable/disable), the buffer memory contents of all endpoints becomes invalid. therefore, all valid data must be removed from enabled endpoints before changing the con guration. code (hex): 20 to 2f write (control out, control in, endpoint 1 to 14) code (hex): 30 to 3f read (control out, control in, endpoint 1 to 14) transaction write or read 1 byte (code or data) table 108: dcendpointcon guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 109: dcendpointcon guration register: bit description bit symbol description 7 fifoen logic 1 indicates an enabled buffer memory with allocated memory. logic 0 indicates a disabled buffer memory (no bytes allocated). 6 epdir this bit de nes the endpoint direction (0 = out, 1 = in); it also determines the dma transfer direction (0 = read, 1 = write). 5 dblbuf logic 1 indicates that this endpoint has double buffering. 4 ffoiso logic 1 indicates an isochronous endpoint. logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] selects the buffer memory size according to ta b l e 1 5 .
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 114 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.1.2 dcaddress register (r/w: b7h/b6h) this command is used to set the usb assigned address in the dcaddress register and enable the usb device. the dcaddress register bit allocation is shown in table 110 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the dcaddress register (accessible by the microprocessor) is not altered by the bus reset. in response to the standard usb request set address, the rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write or read dcaddress register transaction write or read 1 byte (code or data) 16.1.3 dcmode register (r/w: b9h/b8h) this command is used to access the dcmode register, which consists of 1 byte (bit allocation: see table 112 ). in the 16-bit bus mode, the upper byte is ignored. the dcmode register controls the dma bus width, the resume and suspend modes, interrupt activity, and softconnect operation. it can be used to enable the debug mode, in which all errors and not acknowledge (nak) conditions will generate an interrupt. code (hex): b8/b9 write or read dcmode register transaction write or read 1 byte (code or data) [1] unchanged by a bus reset. table 110: dcaddress register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 111: dcaddress register: bit description bit symbol description 7 deven logic 1 enables the device. 6 to 0 devadr[6:0] this eld speci es the usb device address. table 112: dcmode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved gosusp reserved intena dbgmod reserved softct reset 1 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 115 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.1.4 dchardwarecon guration register (r/w: bbh/bah) this command is used to access the dchardwarecon guration register, which consists of two bytes. the rst (lower) byte contains the device con guration and control values, the second (upper) byte holds the clock control bits and the clock division factor. the bit allocation is given in table 114 . a bus reset will not change any of the programmed bit values. the dchardwarecon guration register controls the connection to the usb bus, clock activity and power supply during the suspend state, as well as output clock frequency, dma operating mode and pin con gurations (polarity, signalling mode). code (hex): ba/bb write or read dchardwarecon guration register transaction write or read 2 bytes (code or data) table 113: dcmode register: bit description bit symbol description 7 to 6 - reserved 5 gosusp writing logic 1 followed by logic 0 will activate the suspend mode. 4 - reserved 3 intena logic 1 enables all interrupts. bus reset value: unchanged. 2 dbgmod logic 1 enables debug mode, in which all naks and errors will generate an interrupt. logic 0 selects normal operation, in which interrupts are generated on every ack (bulk endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct logic 1 enables softconnect. this bit is ignored if extpul = 1 in the dchardwarecon guration register (see table 114 ). bus reset value: unchanged. remark: in the otg mode, this bit is ignored. the loc_conn bit of the otgcontrol register controls the pull-up resistor on the otg_dp1 pin. table 114: dchardwarecon guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul nolazy clkrun ckdiv[3:0] reset - 0100011 access - r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol reserved wkupcs reserved intlvl intpol reset 01000100 access r/w r/w r/w - r/w r/w r/w r/w
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 116 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.1.5 dcinterruptenable register (r/w: c3h/c2h) this command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, sof lost, eot, suspend, resume, reset). a bus reset will not change any of the programmed bit values. the command accesses the dcinterruptenable register, which consists of 4 bytes. the bit allocation is given in table 116 . table 115: dchardwarecon guration register: bit description bit symbol description 15 - reserved 14 extpul logic 1 indicates that an external 1.5 k ? pull-up resistor is used on pin otg_dp1 (in the device mode) and that softconnect is not used. bus reset value: unchanged. 13 nolazy logic 1 disables output on pin clkout of the lazyclock frequency (115 khz 50 %) during the suspend state. logic 0 causes pin clkout to switch to lazyclock output after approximately 2 ms delay, following the setting of bit gosusp of the dcmode register. bus reset value: unchanged. 12 clkrun logic 1 indicates that the internal clocks are always running, even during the suspend state. logic 0 switches off the internal oscillator and pll, when they are not needed. during the suspend state, this bit must be made logic 0 to meet the suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp of the dcmode register. bus reset value: unchanged. 11 to 8 ckdiv[3:0] this eld speci es the clock division factor n, which controls the clock frequency on output clkout. the output frequency in mhz is given by . the clock frequency range is 3 mhz to 48 mhz (n = 0 to 15), with a reset value of 12 mhz (n = 3). the hardware design guarantees no glitches during frequency change. bus reset value: unchanged. 7 dakoly logic 1 selects the dack-only dma mode. logic 0 selects the 8237 compatible dma mode. bus reset value: unchanged. 6 drqpol selects the dreq2 pin signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 5 dakpol selects the d a ck2 pin signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 4 - reserved 3 wkupcs logic 1 enables remote wake-up using a low level on input cs. bus reset value: unchanged. 2 - reserved 1 intlvl selects the interrupt signalling mode on output (0 = level; 1 = pulsed). in the pulsed mode, an interrupt produces 166 ns pulse. bus reset value: unchanged. 0 intpol selects the int2 signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 48 n 1 + () ?
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 117 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): c2/c3 write or read interruptenable register transaction write or read 4 bytes (code or data) 16.1.6 dcdmacon guration (r/w: f1h/f0h) this command de nes the dma con guration of the dc and enables or disables dma transfers. the command accesses the dcdmacon guration register, which consists of two bytes. the bit allocation is given in table 118 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write or read dma con guration transaction write or read 2 bytes (code or data) table 116: dcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved sp_ieeot iepsof iesof ieeot iesusp ieresm ierst reset - 0000000 access - r/w r/w r/w r/w r/w r/w r/w table 117: dcinterruptenable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 to 10 iep14 to iep1 logic 1 enables interrupts from the indicated endpoint. 9 iep0in logic 1 enables interrupts from the control in endpoint. 8 iep0out logic 1 enables interrupts from the control out endpoint. 7 - reserved 6 sp_ieeot logic 1 enables interrupt upon detection of a short packet. 5 iepsof logic 1 enables 1 ms interrupts upon detection of pseudo sof. 4 iesof logic 1 enables interrupt upon the sof detection. 3 ieeot logic 1 enables interrupt upon the eot detection. 2 iesusp logic 1 enables interrupt upon detection of a suspend state. 1 ieresm logic 1 enables interrupt upon detection of a resume state. 0 ierst logic 1 enables interrupt upon detection of a bus reset.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 118 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] unchanged by a bus reset. 16.1.7 dcdmacounter register (r/w: f3h/f2h) this command accesses the dcdmacounter register, which consists of two bytes. the bit allocation is given in table 120 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change the programmed bit values. the internal dma counter is automatically reloaded from the dcdmacounter register when dma is re-enabled (dmaen = 1). see section 16.1.6 for more details. code (hex): f2/f3 write or read dcdmacounter register transaction write or read 2 bytes (code or data) table 118: dcdmacon guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reset 0 [1] 0 [1] ------ access r/wr/w------ bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dmaen reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 0-0 [1] 0 [1] access r/w r/w r/w r/w r/w - r/w r/w table 119: dcdmacon guration register: bit description bit symbol description 15 cntren logic 1 enables the generation of an eot condition, when the dcdmacounter register reaches zero. bus reset value: unchanged. 14 shortp logic 1 enables the short or empty packet mode. when receiving (out endpoint) a short or empty packet, an eot condition is generated. when transmitting (in endpoint), this bit should be cleared. bus reset value: unchanged. 13 to 8 - reserved 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see ta b l e 1 7 . 3 dmaen writing logic 1 enables dma transfer, logic 0 forces the end of an ongoing dma transfer. reading this bit indicates whether dma is enabled (0 = dma stopped; 1 = dma enabled). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes) bus reset value: unchanged.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 119 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.1.8 reset device (f6h) this command resets the dc in the same way as an external hardware reset by using the input reset. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none (code only) 16.2 data ow commands data ow commands are used to manage the data transmission between the usb endpoints and the system microprocessor. much of the data ow is initiated using an interrupt to the microprocessor. the data ow commands are used to access the endpoints and determine whether the endpoint buffer memory contains valid data. remark: the in buffer of an endpoint contains input data for the host. the out buffer receives output data from the host. 16.2.1 write or read endpoint buffer (r/w: 10h,12h 1fh/01h 0fh) this command is used to access endpoint buffer memory for reading or writing. first, the buffer pointer is reset to the beginning of the buffer. following the command, a maximum of (n + 2) bytes can be written or read, n representing the size of the endpoint buffer. for 16-bit access, the maximum number of words is (m + 1), with m given by (n + 1) divided by 2. after each read or write action, the buffer pointer is automatically incremented by two. in direct memory access (dma), the rst two bytes or the rst word (the packet length) are skipped: transfers start at the third byte or the second word of the endpoint buffer. when reading, the dc can detect the last byte or word by using the eop condition. when writing to a bulk or interrupt endpoint, the endpoint buffer must be completely lled before sending data to the host. exception: when a dma transfer is stopped by an external eot condition, the current buffer content (full or not) is sent to the host. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command data will cause unpredictable behavior of the dc. table 120: dcdmacounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacr[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 121: dcdmacounter register: bit description bit symbol description 15 to 0 dmacr[15:0] dcdmacounter register
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 120 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): 01 to 0f write (control in, endpoint 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoint 1 to 14) transaction write or read maximum n + 2 bytes (isochronous endpoint: n 1023, bulk/interrupt endpoint: n 32) (code or data) the data in the endpoint buffer memory must be organized as shown in table 122 .an example of endpoint buffer memory access is given in table 123 . remark: there is no protection against writing or reading past a buffer s boundary, against writing into an out buffer or reading from an in buffer. any of these actions could cause an incorrect operation. data residing in an out buffer is only meaningful after a successful transaction. exception: during dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 16.2.2 read endpoint status (r: 50h 5fh) this command is used to read the status of an endpoint buffer memory. the command accesses the dcendpointstatus register, the bit allocation of which is shown in table 124 . reading the dcendpointstatus register will clear the interrupt bit set for the corresponding endpoint in the dcinterrupt register (see table 140 ). all bits of the dcendpointstatus register are read-only. bit epstal is controlled by the stall or unstall commands and by the reception of a set-up token (see section 16.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoint 1 to 14) transaction read 1 byte (code only) table 122: endpoint buffer memory organization word # description 0 (lower byte) packet length (lower byte) 0 (upper byte) packet length (upper byte) 1 (lower byte) data byte 1 1 (upper byte) data byte 2 m = (n + 1)/2 data byte n table 123: example of endpoint buffer memory access a0 phase bus lines word # description high command d[7:0] - command code (00h to 1fh) d[15:8] - ignored low data d[15:0] 0 packet length low data d[15:0] 1 data word 1 (data byte 2, data byte 1) low data d[15:0] 2 data word 2 (data byte 4, data byte 3)
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 121 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.2.3 stall endpoint or unstall endpoint (40h 4fh/80h 8fh) these commands are used to stall or unstall an endpoint. the commands modify the content of the dcendpointstatus register (see table 124 ). a stalled control endpoint is automatically unstalled when it receives a set-up token, regardless of the packet content. if the endpoint should stay in its stalled state, the microprocessor can re-stall it with the stall endpoint command. when a stalled endpoint is unstalled (either by using the unstall endpoint command or by receiving a set-up token), it is also re-initialized. this ushes the buffer: if it is an out buffer, it waits for a data 0 pid; if it is an in buffer, it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoint 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoint 1 to 14) transaction none (code only) table 124: dcendpointstatus register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 0000000 - access rrrrrrr - table 125: dcendpointstatus register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). set to logic 1 by a stall endpoint command, cleared to logic 0 by an unstall endpoint command. the endpoint is automatically unstalled on receiving a set-up token. 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data pid; 1 = data1 pid). 3 overwrite this bit is set by hardware. logic 1 indicates that a new set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the set-up data has nished. firmware must check this bit before sending an acknowledge set-up command or stalling the endpoint. upon reading logic 1, the rmware must stop ongoing set-up actions and wait for a new set-up packet. 2 setupt logic 1 indicates that the buffer contains a set-up packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer; 1 = secondary buffer). 0 - reserved
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 122 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.2.4 validate endpoint buffer (61h 6fh) this command signals the presence of valid data for transmission to the usb host, by setting the buffer full ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint, this command switches the current buffer memory for cpu access. remark: for special aspects of the control in endpoint, see section 13.3.6 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoint 1 to 14) transaction none (code only) 16.2.5 clear endpoint buffer (70h, 72h 7fh) this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint, this command switches the current buffer memory for cpu access. remark: for special aspects of the control out endpoint, see section 13.3.6 . code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoint 1 to 14) transaction none (code only) 16.2.6 dcendpointstatusimage register (d0h dfh) this command is used to check the status of the selected endpoint buffer memory without clearing any status or interrupt bits. the command accesses the dcendpointstatusimage register, which contains a copy of the dcendpointstatus register. the bit allocation of the dcendpointstatusimage register is shown in table 126 . code (hex): d0 to df check status (control out, control in, endpoint 1 to 14) transaction write or read 1 byte (code or data) table 126: dcendpointstatusimage register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 0000000 - access rrrrrrr - table 127: dcendpointstatusimage register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data0 pid; 1 = data1 pid).
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 123 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.2.7 acknowledge set-up (f4h) this command acknowledges to the host that a set-up packet was received. the arrival of a set-up packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor needs to re-enable these commands by sending an acknowledge set-up command, see section 13.3.6 . code (hex): f4 acknowledge set-up transaction none (code only) 16.3 general commands 16.3.1 read endpoint error code (r: a0h afh) this command returns the status of the last transaction of the selected endpoint, as stored in the dcerrorcode register. each new transaction overwrites the previous status information. the bit allocation of the dcerrorcode register is shown in table 128 . code (hex): a0 to af read error code (control out, control in, endpoint 1 to 14) transaction read 1 byte (code or data) 3 overwrite this bit is set by hardware. logic 1 indicates that a new set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the set-up data has nished. firmware must check this bit before sending an acknowledge set-up command or stalling the endpoint. upon reading logic 1, the rmware must stop ongoing set-up actions and wait for a new set-up packet. 2 setupt logic 1 indicates that the buffer contains a set-up packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer; 1 = secondary buffer). 0 - reserved table 127: dcendpointstatusimage register: bit description continued bit symbol description table 128: dcerrorcode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00 - 00000 access rr - rrrrr table 129: dcerrorcode register: bit description bit symbol description 7 unread logic 1 indicates that a new event occurred before the previous status was read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid; 1 = data1 pid).
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 124 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.3.2 unlock device (b0h) this command unlocks the dc from write-protection mode after a resume . in the suspend state, all registers and buffer memory are write-protected to prevent data corruption by external devices during a resume . also, the register access for reading is possible only after the unlock device command is executed. after waking up from the suspend state, the rmware must unlock the registers and buffer memory by using this command, by writing the unlock code (aa37h) into the dclock register (8-bit bus: lower byte rst). the bit allocation of the dclock register is given in table 131 . code (hex): b0 unlock the device transaction write 2 bytes (unlock code) (code or data) 5 - reserved 4 to 1 error[3:0] error code. for error description, see table 130 . 0 rtok logic 1 indicates that data was successfully received or transmitted. table 130: transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data or acknowledge) or is a set-up token to a non-control endpoint 0100 token crc error 0101 data crc error 0110 time-out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored table 129: dcerrorcode register: bit description continued bit symbol description table 131: dclock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlock[15:8] = aah reset 10101010 access wwwwwwww
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 125 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.3.3 dcscratch register (r/w: b3h/b2h) this command accesses the 16-bit dcscratch register, which can be used by the rmware to save and restore information. for example, the device status before powering down in the suspend state. the register bit allocation is given in table 133 . code (hex): b2/b3 write or read dcscratch register transaction write or read 2 bytes (code or data) 16.3.4 dcframenumber register (r: b4h) this command returns the frame number of the last successfully received sof. it is followed by reading one word from the dcframenumber register, containing the frame number. the dcframenumber register is shown in table 135 . remark: after a bus reset, the value of the dcframenumber register is unde ned. code (hex): b4 read frame number transaction read 1 or 2 bytes (code or data) bit 7 6 5 4 3 2 1 0 symbol unlock[7:0] = 37h reset 00110111 access wwwwwwww table 132: dclock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks the internal registers and buffer memory for writing, following a resume . table 133: dcscratch information register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sfir[12:8] reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfir[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 134: dcscratch information register: bit description bit symbol description 15 to 13 - reserved; must be logic 0 12 to 0 sfir[12:0] scratch information register
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 126 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] reset value unde ned after a bus reset. 16.3.5 dcchipid (r: b5h) this command reads the chip identi cation code and hardware version number. the rmware must check this information to determine the supported functions and features. this command accesses the dcchipid register, which is shown in table 138 . code (hex): b5 read chip id transaction read 2 bytes (code or data) table 135: dcframenumber register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sofr[9:8] reset [1] -----000 access -----rrr bit 7 6 5 4 3 2 1 0 symbol sofr[7:0] reset [1] 00000000 access rrrrrrrr table 136: dcframenumber register: bit description bit symbol description 15 to 11 - reserved 10 to 0 sofr[9:0] frame number table 137: example of dcframenumber register access a0 phase bus lines word # description high command d[15:8] - ignored d[7:0] - command code (b4h) low data d[15:0] 0 frame number table 138: dcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 00110110 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset 00110000 access rrrrrrrr
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 127 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16.3.6 dcinterrupt register (r: c0h) this command indicates the sources of interrupts as stored in the 4-byte dcinterrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the dcinterrupt register is shown in table 140 . bit bustatus is used to verify the current bus status in the interrupt service routine. interrupts are enabled using the dcinterruptenable register, see section 16.1.5 . while reading the dcinterrupt register, it is recommended that both 2-byte words are read completely. code (hex): c0 read dcinterrupt register transaction read 4 bytes (code or data) table 139: dcchipid register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (36h) 7 to 0 chipidl[7:0] silicon version (30h, with 30 representing the bcd encoded version number) table 140: dcinterrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus sp_eot psof sof eot suspnd resume reset reset 00000000 access rrrrrrrr table 141: dcinterrupt register: bit description bit symbol description 31 to 24 - reserved 23 to 10 ep14 to ep1 logic 1 indicates the interrupt source(s): endpoint 14 to 1. 9 ep0in logic 1 indicates the interrupt source: control in endpoint. 8 ep0out logic 1 indicates the interrupt source: control out endpoint. 7 bustatus monitors the current usb bus status (0 = awake, 1 = suspend). 6 sp_eot logic 1 indicates that an eot interrupt has occurred for a short period.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 128 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5 psof logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after three missed sofs, the suspend state is entered. 4 sof logic 1 indicates that an sof condition was detected. 3 eot logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume logic 1 indicates that a resume state was detected. 0 reset logic 1 indicates that a bus reset condition was detected. table 141: dcinterrupt register: bit description continued bit symbol description
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 129 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k ? resistor (human body model). 18. recommended operating conditions table 142: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v v i input voltage ? 0.5 +6.0 v i lu latch-up current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <1 a [1] ? 2000 +2000 v t stg storage temperature ? 60 +150 c table 143: recommended operating conditions dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v i input voltage on digital i/o lines 1.8 v tolerant pins 0 1.8 2.0 v 3.3 v tolerant pins 0 3.3 3.6 v 5 v tolerant pins 0 5.0 5.5 v v i(ai/o) input voltage on analog i/o lines (pins dp and dm) 0 - 3.6 v v o(od) open-drain output pull-up voltage 5 v tolerant pins 0 - 5.5 v non 5 v tolerant pins 0 - 3.6 v t amb ambient temperature ? 40 - +85 c
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 130 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19. static characteristics [1] power consumption on the charge pump is not included. [1] not applicable for open-drain outputs. [2] these values are applicable to transistor inputs. the value will be different if internal pull-up or pull-down resistors are used. table 144: static characteristics: supply pins v cc = 3.3 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; unless otherwise speci ed. symbol parameter conditions min typ max unit i cc(hc ) operating supply current for the hc dc suspended - 33 - ma i cc(dc ) operating supply current for the dc hc suspended - 20 - ma i cc(hc+dc ) operating supply current for the host and the device -50- ma i cc(susp ) suspend supply current hc and dc are suspended [1] -60- a table 145: static characteristics: digital pins v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; unless otherwise speci ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt-trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = 4 ma - - 0.4 v i ol =20 a - - 0.1 v v oh high-level output voltage i oh =4ma [1] 2.4 - - v i oh =20 av cc ? 0.1 - - v leakage current i li input leakage current [2] ? 5- + 5 a c in pin capacitance pin to gnd - - 5 pf open-drain outputs i oz off-state output current ? 5- + 5 a
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 131 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. d + is the usb positive data line and d ? is the usb negative data line. [2] includes external resistors of 18 ? 10% on h_dp2 and h_dm2, and 27 ? 10% on otg_dp1 and otg_dm1. [3] in the suspend mode, the minimum voltage is 2.7 v. table 146: static characteristics: analog i/o pins (d + ,d ? ) [1] v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; unless otherwise speci ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d + ) ? v i(d ? ) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k ? to + 3.6 v - - 0.3 v v oh high-level output voltage r l =15k ? to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current ? 10 - + 10 a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance r pd(otg) pull-down resistance on pins otg_dp1 and otg_dm1 enable internal resistors 14.25 - 24.8 k ? r pd(h) pull-down resistance on pins h_dp2 and h_dm2 enable internal resistors 10 - 20 k ? r pu(otg) pull-up resistance on otg_dp1 bus idle 900 - 1575 ? bus driven 1425 - 3090 ? z drv driver output impedance steady-state drive [2] 29 - 44 ? z inp input impedance 10 - - m ? termination v term termination voltage for upstream port pull up (r pu ) [3] 3.0 - 3.6 v table 147: static characteristics: charge pump v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; c load = 2 f ; unless otherwise speci ed. symbol parameter conditions min typ max unit v bus regulated v bus voltage i load = 8 ma from v bus(otg) ; see figure 29 - 5 5.25 v i load maximum load current external capacitor of 27 nf; v cc = 3.0 v to 3.6 v --8ma external capacitor of 82 nf; v cc = 3.0 v to 3.3 v - - 14 ma external capacitor of 82 nf; v cc = 3.3 v to 3.6 v - - 20 ma c load output capacitance 1 - 6.5 f v bus(leak) v bus(otg) leakage voltage v bus(otg) not driven - - 0.2 v
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 132 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. i cc(cp)(susp) suspend supply current for charge pump globalpowerdown bit of the hchardwarecon guration register is logic 0 --45 a globalpowerdown bit of the hchardwarecon guration register is logic 1 --15 a i cc(cp) operating supply current in charge pump mode atx is idle i load = 8 ma - - 20 ma i load = 0 ma - - 300 a v th(vbus_vld) v bus valid threshold 4.4 - - v v th(sess_end) v bus session end threshold 0.2 - 0.8 v v hys(sess_end) v bus session end hysteresis - 150 - mv v th(asess_vld) v bus a valid threshold 0.8 - 2 v v hys(asess_vld) v bus a valid hysteresis - 200 - mv v th(bsess_vld) v bus b valid threshold 2 - 4 v v hys(bsess_vld) v bus b valid hysteresis - 200 - mv eef ciency when loaded i load = 8 ma; v in =3v; see figure 28 -75-% i vbus(leak) leakage current from v bus -15- a r vbus(pu) v bus pull-up resistance pull to v cc when enabled 281 - - ? r vbus(pd) v bus pull-down resistance pull to gnd when enabled 656 - - ? r vbus(idle) v bus idle impedance for the a-device when id = low and drv_vbus = 0 40 - 100 k ? r vbus(active) v bus active pull-down impedance when id = high and drv_vbus =1 - 350 - k ? table 147: static characteristics: charge pump continued v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; c load = 2 f ; unless otherwise speci ed. symbol parameter conditions min typ max unit
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 133 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 82 nf charge pump capacitor. fig 28. ef ciency versus load current. 25 100 0 0 5 15 20 i load (ma) 10 20 40 60 80 e efficiency (%) 004aaa211 v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v 82 nf charge pump capacitor. fig 29. output voltage versus load current. 25 4.6 01015 v bus (v) 5 20 i load (ma) 4.7 4.8 4.9 5.0 5.1 5.2 5.3 004aaa212 v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 134 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [2] tolerance of the clock frequency is 50 ppm. [1] dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. test circuit. [2] excluding the rst transition from the idle state. [3] characterized only, not tested. limits guaranteed by design. table 148: dynamic characteristics v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; unless otherwise speci ed. symbol parameter conditions min typ max unit reset t w( reset) pulse width on input reset crystal oscillator running 10 - - ms crystal oscillator stopped [1] ---ms crystal oscillator f xtal crystal frequency [2] - 12 - mhz r s series resistance - - 100 ? c load load capacitance c x1 , c x2 = 22 pf - 12 - pf external clock input j external clock jitter - - 500 ps t duty clock duty cycle 45 50 55 % t cr , t cf rise time and fall time - - 3 ns table 149: dynamic characteristics: analog i/o lines (d + ,d ? ) [1] v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; c l = 50 pf; r pu = 1.5 k ? 5 % on dp to v term ; unless otherwise speci ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l = 50 pf; 10% to 90% of | v oh ? v ol | 4 - 20 ns t ff fall time c l = 50 pf; 90% to 10% of | v oh ? v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2][3] 1.3 - 2.0 v table 150: dynamic characteristics: charge pump v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; c load =2 f; unless otherwise speci ed. symbol parameter conditions min typ max unit driver characteristics t start-up rise time to v bus = 4.4 v i load = 8 ma; c load =10 f - - 100 ms t comp_clk clock period 1.5 - 3 s
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 135 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.1 programmed i/o timing if you are accessing only the hc, then the hc programmed i/o timing applies. if you are accessing only the dc, then the dc programmed i/o timing applies. if you are accessing both the hc and the dc, then the dc programmed i/o timing applies. 20.1.1 hc programmed i/o timing t vbus(valid_dly) minimum time v bus(valid) error 100 - 200 s t vbus(pulse) v bus pulsing time 10 - 30 ms t vbus(valid_dly) v bus pull-down time 50 - - ms v ripple output ripple with constant load i load =8ma --50mv table 150: dynamic characteristics: charge pump continued v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = ? 40 cto + 85 c; c load =2 f; unless otherwise speci ed. symbol parameter conditions min typ max unit table 151: dynamic characteristics: hc programmed interface timing symbol parameter conditions min typ max unit t as address set-up time before cs 5 - - ns t ah address hold time after cs 2 - - ns read timing t shsl_r rst rd/wr after command (a0 = high) register access 300 - - ns t shsl_b rst rd/wr after command (a0 = high) buffer access 462 - - ns t slrl cs low to rd low 0 - - ns t rhsh rd high to cs high 0 - - ns t rl rd low pulse width 33 - - ns t rhrl rd high to next rd low 110 - - ns t rc rd cycle 143 - - ns t rhdz rd data hold time - - 3 ns t rldv rd low to data valid - - 22 ns write timing t wl wr low pulse width 26 - - ns t whwl wr high to next wr low 110 - - ns t wc wr cycle 136 - - ns t slwl cs low to wr low 0 - - ns t whsh wr high to cs high 0 - - ns t wdsu wr data set-up time 3 - - ns t wdh wr data hold time 4 - - ns
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 136 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.1.2 dc programmed i/o timing fig 30. hc programmed interface timing. mgt969 a0 d [ 15:0 ] d [ 15:0 ] wr rd cs data valid data valid data valid data valid data valid data valid data valid data valid data valid t shsl t rlrh t rhrl t rldv t wl t whwl t wdh t wdsu t rc t wc t rhdz t slrl t rhsh t slwl t whsh t ah t as table 152: dynamic characteristics: dc programmed interface timing symbol parameter conditions min typ max unit read timing (see figure 31 ) t rhax address hold time after rd high 0 - - ns t avrl address set-up time before rd low 0 - - ns t shdz data outputs high-impedance time after cs high --3ns t rhsh chip deselect time after rd high 0 - - ns t rlrh rd pulse width 25 - - ns t rldv data valid time after rd low - - 22 ns t shrl cs high until next isp1362 rd 120 - - ns t shrl +t rlrh +t rhsh read cycle time 180 - - ns write timing (see figure 32 ) t whax address hold time after wr high 1 - - ns t avwl address set-up time before wr low 0 - - ns t shwl cs high until next isp1362 wr 120 - - ns t shwl +t wlwh +t whsh write cycle time [1] 180 - - ns t wlwh wr pulse width 22 - - ns
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 137 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] in the command to data phase, the minimum value of the write command to the read data or write data cycle time should be 205 ns. t whsh chip deselect time after wr high 0 - - ns t dvwh data set-up time before wr high 5 - - ns t whdz data hold time after wr high 3 - - ns table 152: dynamic characteristics: dc programmed interface timing continued symbol parameter conditions min typ max unit (1) for t shrl both cs and rd must be deasserted. (2) programmable polarity: shown as active low. fig 31. dc programmed interface read timing (i/o and 8237 compatible dma). 004aaa105 a0 t rhax t avrl t rlrh t rldv t shdz t shrl (1) d[15:0] rd cs/dack2 (2) t rhsh
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 138 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2 dma timing 20.2.1 hc single-cycle dma timing [1] t rhal +t ds +t alrl (1) for t shwl both cs and wr must be deasserted. (2) programmable polarity: shown as active low. fig 32. dc programmed interface write timing (i/o and 8237 compatible dma). 004aaa106 cs/dack2 (2) a0 d[15:0] wr t whax t avwl t whdz t dvwh t wlwh t whsh t shwl (1) table 153: dynamic characteristics: hc single-cycle dma timing symbol parameter conditions min typ max unit read/write timing t rl rd pulse width 33 - - ns t rldv read process data set-up time 30 - - ns t rhdz read process data hold time 0 - - ns t wsu write process data set-up time 5 - - ns t whd write process data hold time 0 - - ns t ahrh d a ck1 high to dreq1 high 72 - - ns t alrl d a ck1 low to dreq1 low - - 21 ns t dc dreq1 cycle [1] --ns t shah rd/wr high to d a ck1 high 0 - - ns t rhal dreq1 high to d a ck1 low 0 - - ns t ds dreq1 pulse spacing 146 - - ns
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 139 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.2 hc burst mode dma timing fig 33. hc single-cycle dma timing. 004aaa107 dreq1 dack1 d [ 15:0 ] (read) d [ 15:0 ] (write) rd or wr t ds t ahrh t dc data valid data valid t alrl t rhal t whd t wsu t rldv t rhdz t shah table 154: dynamic characteristics: hc burst mode dma timing symbol parameter conditions min typ max unit read/write timing (for 4-cycle and 8-cycle burst mode) t rl wr/rd low pulse width 42 - - ns t rhrl wr/rd high to next wr/rd low 60 - - ns t rc wr/rd cycle 102 - - ns t slrl rd/wr low to dreq1 low 22 - 64 ns t shah rd/wr high to d a ck1 high 0 - - ns t rhal dreq1 high to d a ck1 low 0 - ns t dc dreq1 cycle [1] --ns
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 140 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] t slal +(4or8)t rc +t ds 20.2.3 dc single-cycle dma timing (8237 mode) t ds(read) dreq1 pulse spacing (read) 4-cycle burst mode 105 - - ns 8-cycle burst mode 150 - - ns t ds(write) dreq1 pulse spacing (write) 4-cycle burst mode 72 - - ns 8-cycle burst mode 167 - - ns table 154: dynamic characteristics: hc burst mode dma timing continued symbol parameter conditions min typ max unit fig 34. hc burst mode dma timing. 004aaa108 t rhrl t ds t rhsh dreq1 dack1 rd or wr t slrl t shah t rlrh t rc t rhal table 155: dynamic characteristics: dc single-cycle dma timing (8237 mode) symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t cy(dreq2) cycle time signal dreq2 180 - - ns (1) programmable polarity: shown as active low. fig 35. dc single-cycle dma timing (8237 mode). 004aaa111 dreq2 dack2 (1) t asrp t rc
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 141 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.4 dc single-cycle dma read timing in dack-only mode 20.2.5 dc single-cycle dma write timing in dack-only mode table 156: dynamic characteristics: dc single-cycle dma read timing in dack-only mode symbol parameter conditions min typ max unit t asrp dreq off after d a ck on - - 40 ns t asap d a ck pulse width 25 - - ns t asap + t aprs dreq on after d a ck off 180 - - ns t asdv data valid after d a ck on - - 22 ns t apdz data hold after d a ck off - - 3 ns (1) programmable polarity: shown as active low. fig 36. dc single-cycle dma read timing in dack-only mode. 004aaa112 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap table 157: dynamic characteristics: dc single-cycle dma write timing in dack-only mode symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t asap d a ck2 pulse width 25 - - ns t asap + t aprs dreq2 on after d a ck2 off 180 - - ns t asdv data valid after d a ck2 on - - 22 ns t apdz data hold after d a ck2 off - - 3 ns
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 142 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.6 dc burst mode dma timing (1) programmable polarity: shown as active low. fig 37. dc single-cycle dma write timing in dack-only mode. 004aaa113 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap table 158: dynamic characteristics: dc burst mode dma timing symbol parameter conditions min typ max unit t rsih input rd/ wr high after dreq on 22 - - ns t ilrp dreq off after input rd/ wr low ---ns t ihap d a ck off after input rd/ wr high 0 - 60 ns t ihil dma burst repeat interval (input rd/ wr high to low) t rl or t wl is 30 ns (min) 160 - - ns (1) programmable polarity: shown as active low. fig 38. dc burst mode dma timing. 004aaa115 dack2 (1) dreq2 t rsih t ilrp t ihil t ihap rd or wr
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 143 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21. package outline fig 39. lqfp64 package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 144 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 40. tfbga64 package outline. ball a1 index area 0.5 a 1 b a 2 unit d y e references outline version european projection issue date 00-11-22 02-04-09 iec jedec jeita mm 1.1 0.25 0.15 0.85 0.75 6.1 5.9 y 1 6.1 5.9 0.35 0.25 0.08 dimensions (mm are the original dimensions) sot543-1 mo-195 - - - - - - e 0.15 0.1 e 1 4.5 e 2 4.5 v 0.05 w 0 2.5 5 mm scale sot543-1 tfbga64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm a max. a a 2 a 1 detail x x d e a b c d e f h j k g 2468910 1357 b a ball a1 index area y y 1 c e e e 1 b c e 2 1/2 e 1/2 e a c c b ? v m ? w m
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 145 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22. soldering 22.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ne pitch smds. in these situations re ow soldering is recommended. in these situations re ow soldering is recommended. 22.2 re ow soldering re ow soldering requires solder paste (a suspension of ne solder particles, ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) for all bga, htsson..t and ssop..t packages for packages with a thickness 2.5 mm for packages with a thickness < 2.5 mm and a volume 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 22.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci cally developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 146 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. for packages with leads on two sides and a pitch (e): larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ux will eliminate the need for removal of corrosive residues in most applications. 22.4 manual soldering fix the component by rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 22.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 159: suitability of surface mount ic packages for wave and re ow soldering methods package [1] soldering method wave re ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 147 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ex foil. however, the image sensor package can be mounted by the client on a ex foil by using a hot bar soldering process. the appropriate soldering pro le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
philips semiconductors isp1362 single-chip usb otg controller product data rev. 04 24 december 2004 148 of 150 9397 750 13957 ? koninklijke philips electronics n.v. 2004. all rights reserved. 23. revision history table 160: revision history rev date cpcn description 04 20041224 200412031 product data (9397 750 13957) modi cations: section 12.8.1 using internal oc detection circuit : changed source to drain and drain to source in the third paragraph second sentence and the gure. table 152 dynamic characteristics: dc programmed interface timing : changed the min value of t rhax from 3 ns to 0 ns and of t whax from 3 ns to 1 ns, and added t shrl and t shwl . 03 20040106 - product data (9397 750 12337) 02 20030219 - product data (9397 750 10767) 01 20021120 - preliminary data (9397 750 10087)
9397 750 13957 philips semiconductors isp1362 single-chip usb otg controller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 24 december 2004 149 of 150 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 24. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 25. de nitions short-form speci cation the data in a short-form speci cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci ed use without further testing or modi cation. 26. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production ), relevant changes will be communicated via a customer product/process change noti cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci ed. 27. trademarks arm is a trademark of arm ltd. dragonball is a trademark of motorola, inc. fujitsu is a registered trademark of fujitsu corp. goodlink is a trademark of koninklijke philips electronics n.v. hitachi is a registered trademark of hitachi ltd. intel is a registered trademark of intel corp. motorola is a registered trademark of motorola, inc. nec is a registered trademark of nec corp. powerpc is a trademark of ibm corp. softconnect is a trademark of koninklijke philips electronics n.v. sparclite is a registered trademark of sparc international. strongarm is a trademark of arm ltd. toshiba is a registered trademark of toshiba corp. level data sheet status [1] product status [2][3] de nition i objective data development this data sheet contains data from the objective speci cation for product development. philips semiconductors reserves the right to change the speci cation in any manner without notice. ii preliminary data quali cation this data sheet contains data from the preliminary speci cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 24 december 2004 document order number: 9397 750 13957 contents philips semiconductors isp1362 single-chip usb otg controller 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 host/peripheral roles . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 functional description . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 on-the-go (otg) controller . . . . . . . . . . . . . . . . . . 13 8.2 advanced philips slave host controller (pshc) . . . 13 8.3 philips device controller (dc) . . . . . . . . . . . . . . . . . 13 8.4 phase-locked loop (pll) clock multiplier . . . . . . . . 13 8.5 usb and otg transceivers . . . . . . . . . . . . . . . . . . . 13 8.6 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . 13 8.7 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.8 dc and hc buffer memory. . . . . . . . . . . . . . . . . . . . 13 8.9 goodlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.10 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 host and device bus interface . . . . . . . . . . . . . . . . . 14 9.1 memory organization . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 pio access mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.4 pio access to internal control registers . . . . . . . . . . 21 9.5 pio access to the buffer memory. . . . . . . . . . . . . . . 24 9.6 setting up a dma transfer . . . . . . . . . . . . . . . . . . . . 26 9.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . 30 11 on-the-go (otg) controller . . . . . . . . . . . . . . . . . . . 31 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.2 dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.3 session request protocol (srp) . . . . . . . . . . . . . . . 33 11.4 host negotiation protocol (hnp) . . . . . . . . . . . . . . . 34 11.5 power saving in the idle state and during wake-up . 38 11.6 current capacity of the otg charge pump . . . . . . . 38 12 usb host controller (hc) . . . . . . . . . . . . . . . . . . . . . 39 12.1 usb states of the hc . . . . . . . . . . . . . . . . . . . . . . . . 39 12.2 usb traf c generation . . . . . . . . . . . . . . . . . . . . . . . 40 12.3 usb ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.4 philips transfer descriptor (ptd). . . . . . . . . . . . . . . 41 12.5 features of the control and bulk transfer (aperiodic transfer) . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.6 features of the interrupt transfer . . . . . . . . . . . . . . . 46 12.7 features of the isochronous (iso) transfer . . . . . . . 46 12.8 overcurrent protection circuit . . . . . . . . . . . . . . . . . . 46 12.9 isp1362 hc power management . . . . . . . . . . . . . . 49 13 usb device controller (dc) . . . . . . . . . . . . . . . . . . . 50 13.1 dc data transfer operation . . . . . . . . . . . . . . . . . . . . 50 13.2 device dma transfer . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3 endpoint description . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4 dc direct memory access (dma) transfer . . . . . . . . 54 13.5 isp1362 dc suspend and resume . . . . . . . . . . . . . . 58 14 otg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.1 otgcontrol register (r/w: 62h/e2h) . . . . . . . . . . . . 60 14.2 otgstatus register (r: 67h) . . . . . . . . . . . . . . . . . . . 62 14.3 otginterrupt register (r/w: 68h/e8h). . . . . . . . . . . . 63 14.4 otginterruptenable register (r/w: 69h/e9h) . . . . . . 66 14.5 otgtimer register (r/w: 6ah/eah) . . . . . . . . . . . . . 67 14.6 otgalttimer register (r/w: 6ch/ech) . . . . . . . . . . . 68 15 hc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15.1 hc control and status registers . . . . . . . . . . . . . . . . 71 15.2 hc frame counter registers. . . . . . . . . . . . . . . . . . . 78 15.3 hc root hub registers . . . . . . . . . . . . . . . . . . . . . . . 82 15.4 hc dma and interrupt control registers . . . . . . . . . . 92 15.5 hc miscellaneous registers . . . . . . . . . . . . . . . . . . . 98 15.6 hc buffer ram control registers . . . . . . . . . . . . . . . . 99 15.7 isochronous (iso) transfer registers. . . . . . . . . . . . 101 15.8 interrupt transfer registers. . . . . . . . . . . . . . . . . . . . 103 15.9 control and bulk transfer (aperiodic transfer) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 16 device controller (dc) registers . . . . . . . . . . . . . . . 110 16.1 initialization commands . . . . . . . . . . . . . . . . . . . . . 113 16.2 data ow commands . . . . . . . . . . . . . . . . . . . . . . . 119 16.3 general commands . . . . . . . . . . . . . . . . . . . . . . . . 123 17 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 18 recommended operating conditions . . . . . . . . . . . 129 19 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130 20 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . 134 20.1 programmed i/o timing. . . . . . . . . . . . . . . . . . . . . . 135 20.2 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 21 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 22 soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 22.1 introduction to soldering surface mount packages . 145 22.2 re ow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 22.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 22.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . 146 22.5 package related soldering information . . . . . . . . . . 146 23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 24 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 25 de nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 26 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 27 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

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